An efficient VLSI architecture for 2-D wavelet image coding with novel image scan
A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as a...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 1999-03, Vol.7 (1), p.56-68 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 7 |
| creator | Lafruit, G. Catthoor, F. Cornelis, J.P.H. De Man, H.J. |
| description | A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line. |
| doi_str_mv | 10.1109/92.748201 |
| format | Article |
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The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. 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The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line.</description><subject>Application specific integrated circuits</subject><subject>Applied sciences</subject><subject>Architecture</subject><subject>Bandwidth</subject><subject>Costs</subject><subject>Discrete wavelet transforms</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Image coding</subject><subject>Image processing</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Solid state devices</topic><topic>Signal processing algorithms</topic><topic>Two dimensional</topic><topic>Vector quantization</topic><topic>Very large scale integration</topic><topic>Wavelet</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lafruit, G.</creatorcontrib><creatorcontrib>Catthoor, F.</creatorcontrib><creatorcontrib>Cornelis, J.P.H.</creatorcontrib><creatorcontrib>De Man, H.J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lafruit, G.</au><au>Catthoor, F.</au><au>Cornelis, J.P.H.</au><au>De Man, H.J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An efficient VLSI architecture for 2-D wavelet image coding with novel image scan</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>1999-03-01</date><risdate>1999</risdate><volume>7</volume><issue>1</issue><spage>56</spage><epage>68</epage><pages>56-68</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. 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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 1999-03, Vol.7 (1), p.56-68 |
| issn | 1063-8210 1557-9999 |
| language | eng |
| recordid | cdi_ieee_primary_748201 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits Applied sciences Architecture Bandwidth Costs Discrete wavelet transforms Electronics Energy consumption Exact sciences and technology Image coding Image processing Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing algorithms Two dimensional Vector quantization Very large scale integration Wavelet |
| title | An efficient VLSI architecture for 2-D wavelet image coding with novel image scan |
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