Analysis on Trapping Kinetics of Stress-Induced Trapped Holes in Gate Dielectric of Amorphous HfInZnO TFT

A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors. A negative threshold voltage (V th ) shift and an anomalous hump were observed in transfer characteristics after the...

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Veröffentlicht in:	IEEE transactions on electron devices 2016-06, Vol.63 (6), p.2398-2404
Hauptverfasser:	Kwon, Dae Woong, Kim, Jang Hyun, Kim, Wandong, Kim, Sang Wan, Lee, Jong-Ho, Park, Byung-Gook
Format:	Artikel
Sprache:	eng
Schlagworte:	C-V analysis on metal-oxide thin-film transistors (TFTs) Contact Electron traps Frequency measurement Gates hafnium-indium-zinc-oxide (HIZO) TFTs Insulators Logic gates Semiconductor devices Silicon dioxide Stress stress-induced trapped hole distribution Stresses Thin film transistors Trapping
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