Analysis on Trapping Kinetics of Stress-Induced Trapped Holes in Gate Dielectric of Amorphous HfInZnO TFT

A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors. A negative threshold voltage (V th ) shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO 2 gate insulator, not by interface state generation. Furthermore, capacitance-voltage (C G -V G ) measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on C G -V G characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the α-HIZO/SiO 2 interface and interfacial SiO 2 in contact with the interface, which induces the negative V th shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the C G -V G characteristics at sufficiently low frequencies.