Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions
A novel neuron circuit using a Cu/Ti/Al 2 O 3 -based conductive-bridge random access memory (CBRAM) device for hardware neural networks that utilize nonvolatile memories as synaptic weights is introduced. The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device...
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Veröffentlicht in: | IEEE transactions on electron devices 2016-06, Vol.63 (6), p.2610-2613 |
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creator | Jun-Woo Jang Attarimashalkoubeh, Behnoush Prakash, Amit Hyunsang Hwang Yoon-Ha Jeong |
description | A novel neuron circuit using a Cu/Ti/Al 2 O 3 -based conductive-bridge random access memory (CBRAM) device for hardware neural networks that utilize nonvolatile memories as synaptic weights is introduced. The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device model based on the measured characteristics of the CBRAM device. The applicability of the neuron is demonstrated by constructing a neural network system and applying it to pattern reconstructions that can recall the original patterns from noisy patterns. With these CBRAM-based neurons, a reduction in the area and power of neuromorphic chips is expected in comparison with CMOS-only neuron implementations. |
doi_str_mv | 10.1109/TED.2016.2549359 |
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The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device model based on the measured characteristics of the CBRAM device. The applicability of the neuron is demonstrated by constructing a neural network system and applying it to pattern reconstructions that can recall the original patterns from noisy patterns. With these CBRAM-based neurons, a reduction in the area and power of neuromorphic chips is expected in comparison with CMOS-only neuron implementations.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2016.2549359</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Biological neural networks ; Circuits ; Computer simulation ; Conductive-bridge random access memory (CBRAM) ; Conductivity ; Current measurement ; Devices ; hardware neural network ; integrate-and-fire neuron ; Integrated circuit modeling ; Neural networks ; Neurons ; Random access memory ; Reconstruction ; Resistors ; Semiconductor device measurement</subject><ispartof>IEEE transactions on electron devices, 2016-06, Vol.63 (6), p.2610-2613</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device model based on the measured characteristics of the CBRAM device. The applicability of the neuron is demonstrated by constructing a neural network system and applying it to pattern reconstructions that can recall the original patterns from noisy patterns. With these CBRAM-based neurons, a reduction in the area and power of neuromorphic chips is expected in comparison with CMOS-only neuron implementations.</description><subject>Biological neural networks</subject><subject>Circuits</subject><subject>Computer simulation</subject><subject>Conductive-bridge random access memory (CBRAM)</subject><subject>Conductivity</subject><subject>Current measurement</subject><subject>Devices</subject><subject>hardware neural network</subject><subject>integrate-and-fire neuron</subject><subject>Integrated circuit modeling</subject><subject>Neural networks</subject><subject>Neurons</subject><subject>Random access memory</subject><subject>Reconstruction</subject><subject>Resistors</subject><subject>Semiconductor device measurement</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1PwzAMhiMEEmNwR-JSiQuXjrhJ0-Q4yviQBkNjO0dZ6k6dunYkLRL_nkybOHCyLT2vZT-EXAMdAVB1v5g8jhIKYpSkXLFUnZABpGkWK8HFKRlQCjJWTLJzcuH9JoyC82RAZp_W1GZVY_SOvWubKK-c7asuWvqqWUd52xS97apvjB9cVawxmo_forJ10YfpOnRNNEfbNr5zeyo0l-SsNLXHq2MdkuXTZJG_xNPZ82s-nsaWKd7FLBMJS1QqjLFmBZlJmEBGOQfJiwQxE9xwqQohirKUUGZScW4YkxJsaUrOhuTusHfn2q8efae3lbdY16bBtvcaJAgaXgQI6O0_dNP2rgnXacgUFVIFOFD0QFnXeu-w1DtXbY370UD13rAOhvXesD4aDpGbQ6RCxD884ymFNGO_UU11iA</recordid><startdate>201606</startdate><enddate>201606</enddate><creator>Jun-Woo Jang</creator><creator>Attarimashalkoubeh, Behnoush</creator><creator>Prakash, Amit</creator><creator>Hyunsang Hwang</creator><creator>Yoon-Ha Jeong</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope><orcidid>https://orcid.org/0000-0001-5773-0192</orcidid></search><sort><creationdate>201606</creationdate><title>Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions</title><author>Jun-Woo Jang ; Attarimashalkoubeh, Behnoush ; Prakash, Amit ; Hyunsang Hwang ; Yoon-Ha Jeong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c394t-376232956aacab17a236e3044184d2ee764a489d66dff81f78944a33881cfaf43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Biological neural networks</topic><topic>Circuits</topic><topic>Computer simulation</topic><topic>Conductive-bridge random access memory (CBRAM)</topic><topic>Conductivity</topic><topic>Current measurement</topic><topic>Devices</topic><topic>hardware neural network</topic><topic>integrate-and-fire neuron</topic><topic>Integrated circuit modeling</topic><topic>Neural networks</topic><topic>Neurons</topic><topic>Random access memory</topic><topic>Reconstruction</topic><topic>Resistors</topic><topic>Semiconductor device measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jun-Woo Jang</creatorcontrib><creatorcontrib>Attarimashalkoubeh, Behnoush</creatorcontrib><creatorcontrib>Prakash, Amit</creatorcontrib><creatorcontrib>Hyunsang Hwang</creatorcontrib><creatorcontrib>Yoon-Ha Jeong</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jun-Woo Jang</au><au>Attarimashalkoubeh, Behnoush</au><au>Prakash, Amit</au><au>Hyunsang Hwang</au><au>Yoon-Ha Jeong</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2016-06</date><risdate>2016</risdate><volume>63</volume><issue>6</issue><spage>2610</spage><epage>2613</epage><pages>2610-2613</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A novel neuron circuit using a Cu/Ti/Al 2 O 3 -based conductive-bridge random access memory (CBRAM) device for hardware neural networks that utilize nonvolatile memories as synaptic weights is introduced. The neuronal operations are designed and proved using SPICE simulations with a Verilog-A device model based on the measured characteristics of the CBRAM device. The applicability of the neuron is demonstrated by constructing a neural network system and applying it to pattern reconstructions that can recall the original patterns from noisy patterns. With these CBRAM-based neurons, a reduction in the area and power of neuromorphic chips is expected in comparison with CMOS-only neuron implementations.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2016.2549359</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0001-5773-0192</orcidid></addata></record> |
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subjects | Biological neural networks Circuits Computer simulation Conductive-bridge random access memory (CBRAM) Conductivity Current measurement Devices hardware neural network integrate-and-fire neuron Integrated circuit modeling Neural networks Neurons Random access memory Reconstruction Resistors Semiconductor device measurement |
title | Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions |
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