Effective cluster assignment for modulo scheduling

Clustering is one solution to the demand for wide issue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while remaining scaleable. Much of the previous work on scheduling for clustered architectures has focused on acyclic code. While...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Nystrom, E., Eichenberger, A.E.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 114
container_issue
container_start_page 103
container_title
container_volume
creator Nystrom, E.
Eichenberger, A.E.
description Clustering is one solution to the demand for wide issue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while remaining scaleable. Much of the previous work on scheduling for clustered architectures has focused on acyclic code. While minimizing schedule length of acyclic code is paramount, the primary objective when scheduling cyclic code is to maximize the throughput or steady state performance. This paper investigates a pre-modulo scheduling pass that performs cluster assignment in a way that minimizes performance degradation due to explicit communication required as the loops are split over clusters. The proposed cluster assignment algorithm annotates and adjusts the graph for use by the scheduler so that any traditional modulo scheduling algorithm, having no knowledge of clustering, can produce a valid and efficient schedule for a clustered machine.
doi_str_mv 10.1109/MICRO.1998.742773
format Conference Proceeding
fullrecord <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_742773</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>742773</ieee_id><sourcerecordid>27517680</sourcerecordid><originalsourceid>FETCH-LOGICAL-i203t-e265cdd8c91aaa10539885a5548be15ea6e5145b73cd20b4b97b43a3a8eca5c13</originalsourceid><addsrcrecordid>eNotkEtLw0AURgdUsNb-AF1l5S713nlkZpYSai1UCqLrMJnc1JE8aiYR_PcW4up8i8O3OIzdIawRwT6-7vK3wxqtNWstudbigq2sNmDQZCYDyy_ZAkHzVEqF1-wmxi8AMJlVC8Y3dU1-DD-U-GaKIw2JizEcu5a6Man7IWn7amr6JPpPOo_QHW_ZVe2aSKt_LtnH8-Y9f0n3h-0uf9qngYMYU-KZ8lVlvEXnHIIS1hjllJKmJFTkMlIoVamFrziUsrS6lMIJZ8g75VEs2cP8exr674niWLQhemoa11E_xYJrhTozcBbvZzEQUXEaQuuG32JOIf4A40hSeA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>27517680</pqid></control><display><type>conference_proceeding</type><title>Effective cluster assignment for modulo scheduling</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Nystrom, E. ; Eichenberger, A.E.</creator><creatorcontrib>Nystrom, E. ; Eichenberger, A.E.</creatorcontrib><description>Clustering is one solution to the demand for wide issue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while remaining scaleable. Much of the previous work on scheduling for clustered architectures has focused on acyclic code. While minimizing schedule length of acyclic code is paramount, the primary objective when scheduling cyclic code is to maximize the throughput or steady state performance. This paper investigates a pre-modulo scheduling pass that performs cluster assignment in a way that minimizes performance degradation due to explicit communication required as the loops are split over clusters. The proposed cluster assignment algorithm annotates and adjusts the graph for use by the scheduler so that any traditional modulo scheduling algorithm, having no knowledge of clustering, can produce a valid and efficient schedule for a clustered machine.</description><identifier>ISSN: 1072-4451</identifier><identifier>ISBN: 9780818686092</identifier><identifier>ISBN: 081868609X</identifier><identifier>DOI: 10.1109/MICRO.1998.742773</identifier><language>eng</language><publisher>IEEE</publisher><subject>Birth disorders ; Clocks ; Logic ; Registers ; Routing ; Writing</subject><ispartof>Proceedings of the annual International Symposium on Microarchitecture, 1998, p.103-114</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/742773$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/742773$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nystrom, E.</creatorcontrib><creatorcontrib>Eichenberger, A.E.</creatorcontrib><title>Effective cluster assignment for modulo scheduling</title><title>Proceedings of the annual International Symposium on Microarchitecture</title><addtitle>MICRO</addtitle><description>Clustering is one solution to the demand for wide issue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while remaining scaleable. Much of the previous work on scheduling for clustered architectures has focused on acyclic code. While minimizing schedule length of acyclic code is paramount, the primary objective when scheduling cyclic code is to maximize the throughput or steady state performance. This paper investigates a pre-modulo scheduling pass that performs cluster assignment in a way that minimizes performance degradation due to explicit communication required as the loops are split over clusters. The proposed cluster assignment algorithm annotates and adjusts the graph for use by the scheduler so that any traditional modulo scheduling algorithm, having no knowledge of clustering, can produce a valid and efficient schedule for a clustered machine.</description><subject>Birth disorders</subject><subject>Clocks</subject><subject>Logic</subject><subject>Registers</subject><subject>Routing</subject><subject>Writing</subject><issn>1072-4451</issn><isbn>9780818686092</isbn><isbn>081868609X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkEtLw0AURgdUsNb-AF1l5S713nlkZpYSai1UCqLrMJnc1JE8aiYR_PcW4up8i8O3OIzdIawRwT6-7vK3wxqtNWstudbigq2sNmDQZCYDyy_ZAkHzVEqF1-wmxi8AMJlVC8Y3dU1-DD-U-GaKIw2JizEcu5a6Man7IWn7amr6JPpPOo_QHW_ZVe2aSKt_LtnH8-Y9f0n3h-0uf9qngYMYU-KZ8lVlvEXnHIIS1hjllJKmJFTkMlIoVamFrziUsrS6lMIJZ8g75VEs2cP8exr674niWLQhemoa11E_xYJrhTozcBbvZzEQUXEaQuuG32JOIf4A40hSeA</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Nystrom, E.</creator><creator>Eichenberger, A.E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>1998</creationdate><title>Effective cluster assignment for modulo scheduling</title><author>Nystrom, E. ; Eichenberger, A.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-e265cdd8c91aaa10539885a5548be15ea6e5145b73cd20b4b97b43a3a8eca5c13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Birth disorders</topic><topic>Clocks</topic><topic>Logic</topic><topic>Registers</topic><topic>Routing</topic><topic>Writing</topic><toplevel>online_resources</toplevel><creatorcontrib>Nystrom, E.</creatorcontrib><creatorcontrib>Eichenberger, A.E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nystrom, E.</au><au>Eichenberger, A.E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Effective cluster assignment for modulo scheduling</atitle><btitle>Proceedings of the annual International Symposium on Microarchitecture</btitle><stitle>MICRO</stitle><date>1998</date><risdate>1998</risdate><spage>103</spage><epage>114</epage><pages>103-114</pages><issn>1072-4451</issn><isbn>9780818686092</isbn><isbn>081868609X</isbn><abstract>Clustering is one solution to the demand for wide issue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while remaining scaleable. Much of the previous work on scheduling for clustered architectures has focused on acyclic code. While minimizing schedule length of acyclic code is paramount, the primary objective when scheduling cyclic code is to maximize the throughput or steady state performance. This paper investigates a pre-modulo scheduling pass that performs cluster assignment in a way that minimizes performance degradation due to explicit communication required as the loops are split over clusters. The proposed cluster assignment algorithm annotates and adjusts the graph for use by the scheduler so that any traditional modulo scheduling algorithm, having no knowledge of clustering, can produce a valid and efficient schedule for a clustered machine.</abstract><pub>IEEE</pub><doi>10.1109/MICRO.1998.742773</doi><tpages>12</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1072-4451
ispartof Proceedings of the annual International Symposium on Microarchitecture, 1998, p.103-114
issn 1072-4451
language eng
recordid cdi_ieee_primary_742773
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Birth disorders
Clocks
Logic
Registers
Routing
Writing
title Effective cluster assignment for modulo scheduling
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T17%3A53%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Effective%20cluster%20assignment%20for%20modulo%20scheduling&rft.btitle=Proceedings%20of%20the%20annual%20International%20Symposium%20on%20Microarchitecture&rft.au=Nystrom,%20E.&rft.date=1998&rft.spage=103&rft.epage=114&rft.pages=103-114&rft.issn=1072-4451&rft.isbn=9780818686092&rft.isbn_list=081868609X&rft_id=info:doi/10.1109/MICRO.1998.742773&rft_dat=%3Cproquest_6IE%3E27517680%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27517680&rft_id=info:pmid/&rft_ieee_id=742773&rfr_iscdi=true