Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors
The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a...
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| Veröffentlicht in: | IEEE electron device letters 1999-01, Vol.20 (1), p.36-38 |
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| container_end_page | 38 |
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| container_issue | 1 |
| container_start_page | 36 |
| container_title | IEEE electron device letters |
| container_volume | 20 |
| creator | Huang, Kuo-Ching Fang, Yean-Kuen Yaung, Dun-Nian Chen, Chii-Wen Liang, Mong-Song Hsieh, Jang-Cheng Su, Chi-Wen Lee, Kuei-Ying |
| description | The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range. |
| doi_str_mv | 10.1109/55.737566 |
| format | Article |
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Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/55.737566</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Boron ; Capacitance measurement ; Channels ; Chemical technology ; Chemical vapor deposition ; CMOS ; CMOS process ; CMOS technology ; Devices ; Electric variables ; Leakage ; MOSFET circuits ; Rapid thermal annealing ; Semiconductor devices ; Transistors ; Tungsten</subject><ispartof>IEEE electron device letters, 1999-01, Vol.20 (1), p.36-38</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c408t-d13fec21061ac2c55c5c4893b58875f8b795f86329d1baf5612a3804d27795f93</citedby><cites>FETCH-LOGICAL-c408t-d13fec21061ac2c55c5c4893b58875f8b795f86329d1baf5612a3804d27795f93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/737566$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/737566$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huang, Kuo-Ching</creatorcontrib><creatorcontrib>Fang, Yean-Kuen</creatorcontrib><creatorcontrib>Yaung, Dun-Nian</creatorcontrib><creatorcontrib>Chen, Chii-Wen</creatorcontrib><creatorcontrib>Liang, Mong-Song</creatorcontrib><creatorcontrib>Hsieh, Jang-Cheng</creatorcontrib><creatorcontrib>Su, Chi-Wen</creatorcontrib><creatorcontrib>Lee, Kuei-Ying</creatorcontrib><title>Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range.</description><subject>Annealing</subject><subject>Boron</subject><subject>Capacitance measurement</subject><subject>Channels</subject><subject>Chemical technology</subject><subject>Chemical vapor deposition</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Devices</subject><subject>Electric variables</subject><subject>Leakage</subject><subject>MOSFET circuits</subject><subject>Rapid thermal annealing</subject><subject>Semiconductor devices</subject><subject>Transistors</subject><subject>Tungsten</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqN0TtPwzAQAGALgUQpDKxMnkAMKX7ErxFVvKSiDsAcuc6FBqVOsF0kRv45bosYEYtt6b670_kQOqVkQikxV0JMFFdCyj00okLoggjJ99GIqJIWnBJ5iI5ifCOElqUqR-jrpmnApYj7BtdtfgfwCae1f40JPB767tO1NeAh9A5iZh6nJWDYZrUfgN3Seg8d7sC_piW2vsYDhKYPK-sdbMsCDDiuF6vWhZw-fZw_4RSsj21MfYjH6KCxXYSTn3uMXm5vnqf3xWx-9zC9nhWuJDoVNeW5JcsTUOuYE8IJV2rDF0JrJRq9UCafkjNT04VthKTMck3KmqlNxPAxutjVzaO8ryGmatVGB11nPfTrWBlqDOVSkSzP_5RMa02ZLP8BmWGSqwwvdzD_QIwBmmoI7cqGz4qSarO3Sohqt7dsz3a2BYBf9xP8BrOlk8c</recordid><startdate>199901</startdate><enddate>199901</enddate><creator>Huang, Kuo-Ching</creator><creator>Fang, Yean-Kuen</creator><creator>Yaung, Dun-Nian</creator><creator>Chen, Chii-Wen</creator><creator>Liang, Mong-Song</creator><creator>Hsieh, Jang-Cheng</creator><creator>Su, Chi-Wen</creator><creator>Lee, Kuei-Ying</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>199901</creationdate><title>Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors</title><author>Huang, Kuo-Ching ; Fang, Yean-Kuen ; Yaung, Dun-Nian ; Chen, Chii-Wen ; Liang, Mong-Song ; Hsieh, Jang-Cheng ; Su, Chi-Wen ; Lee, Kuei-Ying</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c408t-d13fec21061ac2c55c5c4893b58875f8b795f86329d1baf5612a3804d27795f93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Annealing</topic><topic>Boron</topic><topic>Capacitance measurement</topic><topic>Channels</topic><topic>Chemical technology</topic><topic>Chemical vapor deposition</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Devices</topic><topic>Electric variables</topic><topic>Leakage</topic><topic>MOSFET circuits</topic><topic>Rapid thermal annealing</topic><topic>Semiconductor devices</topic><topic>Transistors</topic><topic>Tungsten</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Huang, Kuo-Ching</creatorcontrib><creatorcontrib>Fang, Yean-Kuen</creatorcontrib><creatorcontrib>Yaung, Dun-Nian</creatorcontrib><creatorcontrib>Chen, Chii-Wen</creatorcontrib><creatorcontrib>Liang, Mong-Song</creatorcontrib><creatorcontrib>Hsieh, Jang-Cheng</creatorcontrib><creatorcontrib>Su, Chi-Wen</creatorcontrib><creatorcontrib>Lee, Kuei-Ying</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Huang, Kuo-Ching</au><au>Fang, Yean-Kuen</au><au>Yaung, Dun-Nian</au><au>Chen, Chii-Wen</au><au>Liang, Mong-Song</au><au>Hsieh, Jang-Cheng</au><au>Su, Chi-Wen</au><au>Lee, Kuei-Ying</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>1999-01</date><risdate>1999</risdate><volume>20</volume><issue>1</issue><spage>36</spage><epage>38</epage><pages>36-38</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range.</abstract><pub>IEEE</pub><doi>10.1109/55.737566</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 1999-01, Vol.20 (1), p.36-38 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_ieee_primary_737566 |
| source | IEEE Electronic Library (IEL) |
| subjects | Annealing Boron Capacitance measurement Channels Chemical technology Chemical vapor deposition CMOS CMOS process CMOS technology Devices Electric variables Leakage MOSFET circuits Rapid thermal annealing Semiconductor devices Transistors Tungsten |
| title | Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors |
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