Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs
In network on chips (NoCs) design, reconfiguration of NoC is a very effective option for minimizing power consumption, and Gaussian networks can provide significant advantage over the mesh networks in terms of network diameter, average hop distance and so on. In this paper, based on the special topo...
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Veröffentlicht in: | IEEE transactions on computers 2016-07, Vol.65 (7), p.2134-2142 |
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description | In network on chips (NoCs) design, reconfiguration of NoC is a very effective option for minimizing power consumption, and Gaussian networks can provide significant advantage over the mesh networks in terms of network diameter, average hop distance and so on. In this paper, based on the special topology structure and the static connection rules within Gaussian networks, we present the reconfiguration representation for Gaussian networks and the nature of reconfigurable Gaussian networks. Furthermore, reconfigurable rules of Gaussian networks are proposed to design the constraints for automatic reconfiguration of NoC. |
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Furthermore, reconfigurable rules of Gaussian networks are proposed to design the constraints for automatic reconfiguration of NoC.</description><subject>Algorithm design and analysis</subject><subject>Computer architecture</subject><subject>Computer simulation</subject><subject>Finite element method</subject><subject>Gaussian</subject><subject>Gaussian Network</subject><subject>Heuristic algorithms</subject><subject>Mathematical model</subject><subject>Network on Chip</subject><subject>Network Topologies</subject><subject>Network topology</subject><subject>Networks</subject><subject>Power consumption</subject><subject>Reconfigurable Networks</subject><subject>Reconfiguration</subject><subject>Representations</subject><subject>Routing</subject><subject>System on chip</subject><subject>Topology</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkD1PwzAQhi0EEqUwM7BEYmFJ68_YHiFAqVRAQmW2nORcXEJc7EaIf09QKwame6V73tPpQeic4AkhWE-X5YRiIiaUS10QfoBGRAiZay2KQzTCmKhcM46P0UlKa4xxQbEeofljaKD13SoLLpvZPiVvu-wJtl8hvuc3NkGTvUAdOudXfbRVC3_L0OXlm99kt5D8qkun6MjZNsHZfo7R6_3dsnzIF8-zeXm9yGtG6TZnXAJvqKxZwSnhkile4aamFJysKstE44iCQis3BFIRqnihmHOMau4Yq9gYXe3ubmL47CFtzYdPNbSt7SD0yRBFBddCajagl__QdehjN3xniNRCM8o0GajpjqpjSCmCM5voP2z8NgSbX7VmWZpftWavdmhc7BoeAP5oSSXBQrEfSDVy2Q</recordid><startdate>20160701</startdate><enddate>20160701</enddate><creator>Wu, Yangbing</creator><creator>Zhao, Jianfeng</creator><creator>Chen, Deming</creator><creator>Guo, Donghui</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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subjects | Algorithm design and analysis Computer architecture Computer simulation Finite element method Gaussian Gaussian Network Heuristic algorithms Mathematical model Network on Chip Network Topologies Network topology Networks Power consumption Reconfigurable Networks Reconfiguration Representations Routing System on chip Topology |
title | Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs |
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