The Validation of a Multiprocessor Simulator
In this paper, we present the design and implementation of a multiprocessor simulator written in the language SimCal. We use the simulator to test our scheme to partition a sequential program for parallel execution on a shared memory, asynchronous multiprocessor. The results of the simulations indic...
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description | In this paper, we present the design and implementation of a multiprocessor simulator written in the language SimCal. We use the simulator to test our scheme to partition a sequential program for parallel execution on a shared memory, asynchronous multiprocessor. The results of the simulations indicate that our partitioning scheme can provide significant speed-up by executing the program in parallel. We then execute the partitioned program on an actual multiprocessor and find a high degree of correlation between the simulations and the actual executions. This correlation serves to validate our simulator. We then use the multiprocessor simulator to hypothetically extended the actual multiprocessor and we show that adding more processors will not provide significant improvement in the parallel executions unless the communication structure is also improved to contain more parallelism. |
doi_str_mv | 10.1109/WSC.1993.718109 |
format | Conference Proceeding |
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We use the simulator to test our scheme to partition a sequential program for parallel execution on a shared memory, asynchronous multiprocessor. The results of the simulations indicate that our partitioning scheme can provide significant speed-up by executing the program in parallel. We then execute the partitioned program on an actual multiprocessor and find a high degree of correlation between the simulations and the actual executions. This correlation serves to validate our simulator. We then use the multiprocessor simulator to hypothetically extended the actual multiprocessor and we show that adding more processors will not provide significant improvement in the parallel executions unless the communication structure is also improved to contain more parallelism.</description><identifier>ISBN: 9780780313811</identifier><identifier>ISBN: 078031381X</identifier><identifier>DOI: 10.1109/WSC.1993.718109</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computational modeling ; Computer science ; Discrete event simulation ; Multiprocessing systems ; Parallel processing ; Power system modeling ; Power system reliability ; Sequential analysis ; Testing ; Yarn</subject><ispartof>Proceedings of 1993 Winter Simulation Conference - (WSC '93), 1993, p.625-631</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/718109$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/718109$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Malloy, B.A.</creatorcontrib><title>The Validation of a Multiprocessor Simulator</title><title>Proceedings of 1993 Winter Simulation Conference - (WSC '93)</title><addtitle>WSC</addtitle><description>In this paper, we present the design and implementation of a multiprocessor simulator written in the language SimCal. We use the simulator to test our scheme to partition a sequential program for parallel execution on a shared memory, asynchronous multiprocessor. The results of the simulations indicate that our partitioning scheme can provide significant speed-up by executing the program in parallel. We then execute the partitioned program on an actual multiprocessor and find a high degree of correlation between the simulations and the actual executions. This correlation serves to validate our simulator. We then use the multiprocessor simulator to hypothetically extended the actual multiprocessor and we show that adding more processors will not provide significant improvement in the parallel executions unless the communication structure is also improved to contain more parallelism.</description><subject>Computational modeling</subject><subject>Computer science</subject><subject>Discrete event simulation</subject><subject>Multiprocessing systems</subject><subject>Parallel processing</subject><subject>Power system modeling</subject><subject>Power system reliability</subject><subject>Sequential analysis</subject><subject>Testing</subject><subject>Yarn</subject><isbn>9780780313811</isbn><isbn>078031381X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1993</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLxDAUhQMiKGPXgqv8AFtz82ruUoqPgREXU3Q5ZNIbjHTMkHYW_nsL4-HAx9l8cBi7BdEACHz43HYNIKqmBbfsC1Zh68RSBcoBXLFqmr7FEq2Mse6a3fdfxD_8mAY_p_zDc-Sev53GOR1LDjRNufBtOpxGP-dywy6jHyeq_rli_fNT373Wm_eXdfe4qZMVWKMxXkhJzphIAyqJMFihotXBBQtDaINF0nuyELXVe7BBRS_RCi09aVQrdnfWJiLaHUs6-PK7Oz9Sfwc_P20</recordid><startdate>1993</startdate><enddate>1993</enddate><creator>Malloy, B.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1993</creationdate><title>The Validation of a Multiprocessor Simulator</title><author>Malloy, B.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i609-955a022e855fed93291d603f64c8c61dc7c69e4be61f464b16c3fa296042ae493</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Computational modeling</topic><topic>Computer science</topic><topic>Discrete event simulation</topic><topic>Multiprocessing systems</topic><topic>Parallel processing</topic><topic>Power system modeling</topic><topic>Power system reliability</topic><topic>Sequential analysis</topic><topic>Testing</topic><topic>Yarn</topic><toplevel>online_resources</toplevel><creatorcontrib>Malloy, B.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Malloy, B.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The Validation of a Multiprocessor Simulator</atitle><btitle>Proceedings of 1993 Winter Simulation Conference - (WSC '93)</btitle><stitle>WSC</stitle><date>1993</date><risdate>1993</risdate><spage>625</spage><epage>631</epage><pages>625-631</pages><isbn>9780780313811</isbn><isbn>078031381X</isbn><abstract>In this paper, we present the design and implementation of a multiprocessor simulator written in the language SimCal. We use the simulator to test our scheme to partition a sequential program for parallel execution on a shared memory, asynchronous multiprocessor. The results of the simulations indicate that our partitioning scheme can provide significant speed-up by executing the program in parallel. We then execute the partitioned program on an actual multiprocessor and find a high degree of correlation between the simulations and the actual executions. This correlation serves to validate our simulator. We then use the multiprocessor simulator to hypothetically extended the actual multiprocessor and we show that adding more processors will not provide significant improvement in the parallel executions unless the communication structure is also improved to contain more parallelism.</abstract><pub>IEEE</pub><doi>10.1109/WSC.1993.718109</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record> |
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identifier | ISBN: 9780780313811 |
ispartof | Proceedings of 1993 Winter Simulation Conference - (WSC '93), 1993, p.625-631 |
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language | eng |
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subjects | Computational modeling Computer science Discrete event simulation Multiprocessing systems Parallel processing Power system modeling Power system reliability Sequential analysis Testing Yarn |
title | The Validation of a Multiprocessor Simulator |
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