b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units
Existing timing error models for voltage-scaled functional units ignore the effect of history and correlation among outputs, and the variation in the error behavior at different bit locations. We propose b-HiVE, a model for voltage-scaling-induced timing errors that incorporates these attributes and...
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| creator | Tziantzioulis, G. Gok, A. M. Faisal, S. M. Hardavellas, N. Ogrenci-Memik, S. Parthasarathy, S. |
| description | Existing timing error models for voltage-scaled functional units ignore the effect of history and correlation among outputs, and the variation in the error behavior at different bit locations. We propose b-HiVE, a model for voltage-scaling-induced timing errors that incorporates these attributes and demonstrates their impact on the overall model accuracy. On average across several operations, b-HiVE's estimation is within 1--3% of comprehensive analog simulations, which corresponds to 5--17x higher accuracy (6--10x on average) than error models currently used in approximate computing research. To the best of our knowledge, we present the first bit-level error models of arithmetic units, and the first error models for voltage scaling of bitwise logic operations and floating-point units. |
| doi_str_mv | 10.1145/2744769.2744805 |
| format | Conference Proceeding |
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On average across several operations, b-HiVE's estimation is within 1--3% of comprehensive analog simulations, which corresponds to 5--17x higher accuracy (6--10x on average) than error models currently used in approximate computing research. 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M.</creatorcontrib><creatorcontrib>Faisal, S. M.</creatorcontrib><creatorcontrib>Hardavellas, N.</creatorcontrib><creatorcontrib>Ogrenci-Memik, S.</creatorcontrib><creatorcontrib>Parthasarathy, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tziantzioulis, G.</au><au>Gok, A. M.</au><au>Faisal, S. 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On average across several operations, b-HiVE's estimation is within 1--3% of comprehensive analog simulations, which corresponds to 5--17x higher accuracy (6--10x on average) than error models currently used in approximate computing research. To the best of our knowledge, we present the first bit-level error models of arithmetic units, and the first error models for voltage scaling of bitwise logic operations and floating-point units.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/2744769.2744805</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0738-100X |
| ispartof | 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_ieee_primary_7167289 |
| source | IEEE Electronic Library (IEL) |
| subjects | Accuracy Approximate Computing Computational modeling Computing methodologies -- Modeling and simulation -- Model development and analysis -- Modeling methodologies Correlation Data models Error Modeling Hardware -- Hardware test Hardware -- Robustness History Integrated circuit modeling Timing Voltage Scaling |
| title | b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units |
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