Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMO...

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Veröffentlicht in:	IEEE transactions on electron devices 2015-08, Vol.62 (8), p.2396-2403
Hauptverfasser:	Sunhae Shin, Jang, Esan, Jae Won Jeong, Byung-Gook Park, Kyung Rok Kim
Format:	Artikel
Sprache:	eng
Schlagworte:	Analytical models Band-to-band tunneling (BTBT) CMOS integrated circuits CMOS technology Inverters Logic gates low-power multivalued logic noise margin off-leakage variation (OLV) Semiconductor device modeling standard ternary inverter (STI)
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