Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation
We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized...
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| Veröffentlicht in: | IEEE electron device letters 2015-08, Vol.36 (8), p.790-792 |
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| container_title | IEEE electron device letters |
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| creator | Jae Hyo Park Hyung Yoon Kim Ki Hwan Seok Kiaee, Zohreh Sol Kyu Lee Hee Jae Chae Yong Hee Lee Jae Ho Lee Seung Ki Joo |
| description | We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi 2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT's reliability due to the absent of NiSi 2 at the edges and the large effective channel length and width. |
| doi_str_mv | 10.1109/LED.2015.2438871 |
| format | Article |
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The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi 2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT's reliability due to the absent of NiSi 2 at the edges and the large effective channel length and width.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2015.2438871</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>Contamination ; Geometry ; Logic gates ; Metal-induced lateral crystallization (MILC) ; polysilicon thin-film transistors ; Reliability ; short-channel effect ; Stress ; Thin film transistors</subject><ispartof>IEEE electron device letters, 2015-08, Vol.36 (8), p.790-792</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c216t-f5750b89ae60b132d1b4ace093fb98626f22fadfcf82c2baecf297d14098f8da3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7115047$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7115047$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jae Hyo Park</creatorcontrib><creatorcontrib>Hyung Yoon Kim</creatorcontrib><creatorcontrib>Ki Hwan Seok</creatorcontrib><creatorcontrib>Kiaee, Zohreh</creatorcontrib><creatorcontrib>Sol Kyu Lee</creatorcontrib><creatorcontrib>Hee Jae Chae</creatorcontrib><creatorcontrib>Yong Hee Lee</creatorcontrib><creatorcontrib>Jae Ho Lee</creatorcontrib><creatorcontrib>Seung Ki Joo</creatorcontrib><title>Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi 2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT's reliability due to the absent of NiSi 2 at the edges and the large effective channel length and width.</description><subject>Contamination</subject><subject>Geometry</subject><subject>Logic gates</subject><subject>Metal-induced lateral crystallization (MILC)</subject><subject>polysilicon thin-film transistors</subject><subject>Reliability</subject><subject>short-channel effect</subject><subject>Stress</subject><subject>Thin film transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFOwzAMhiMEEmNwR-KSB6AjTtM2PaKxMaShVTDOlZs4o9C1U9Id9vZ02sTJ9q__8-Fj7B7EBEDkT8vZy0QKSCZSxVpncMFGkCQ6EkkaX7KRyBREMYj0mt2E8CMEKJWpEXMf1Ptu49FS9I7hlxe-MxQCWV50zSHUTW26lq_na-46zxf15psX5Id9i62hR1402KLnn73fm37vhwRbO5xYNcRXO_LY1117y64cNoHuznPMvuaz9XQRLVevb9PnZWQkpH3kkiwRlc6RUlFBLC1UCg2JPHZVrlOZOikdWmeclkZWSMbJPLOgRK6dthiPmTj9Nb4LwZMrd77eoj-UIMqjp3LwVB49lWdPA_JwQmoi-q9nAIlQWfwH9WFlcw</recordid><startdate>201508</startdate><enddate>201508</enddate><creator>Jae Hyo Park</creator><creator>Hyung Yoon Kim</creator><creator>Ki Hwan Seok</creator><creator>Kiaee, Zohreh</creator><creator>Sol Kyu Lee</creator><creator>Hee Jae Chae</creator><creator>Yong Hee Lee</creator><creator>Jae Ho Lee</creator><creator>Seung Ki Joo</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201508</creationdate><title>Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation</title><author>Jae Hyo Park ; Hyung Yoon Kim ; Ki Hwan Seok ; Kiaee, Zohreh ; Sol Kyu Lee ; Hee Jae Chae ; Yong Hee Lee ; Jae Ho Lee ; Seung Ki Joo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c216t-f5750b89ae60b132d1b4ace093fb98626f22fadfcf82c2baecf297d14098f8da3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>Contamination</topic><topic>Geometry</topic><topic>Logic gates</topic><topic>Metal-induced lateral crystallization (MILC)</topic><topic>polysilicon thin-film transistors</topic><topic>Reliability</topic><topic>short-channel effect</topic><topic>Stress</topic><topic>Thin film transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jae Hyo Park</creatorcontrib><creatorcontrib>Hyung Yoon Kim</creatorcontrib><creatorcontrib>Ki Hwan Seok</creatorcontrib><creatorcontrib>Kiaee, Zohreh</creatorcontrib><creatorcontrib>Sol Kyu Lee</creatorcontrib><creatorcontrib>Hee Jae Chae</creatorcontrib><creatorcontrib>Yong Hee Lee</creatorcontrib><creatorcontrib>Jae Ho Lee</creatorcontrib><creatorcontrib>Seung Ki Joo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jae Hyo Park</au><au>Hyung Yoon Kim</au><au>Ki Hwan Seok</au><au>Kiaee, Zohreh</au><au>Sol Kyu Lee</au><au>Hee Jae Chae</au><au>Yong Hee Lee</au><au>Jae Ho Lee</au><au>Seung Ki Joo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2015-08</date><risdate>2015</risdate><volume>36</volume><issue>8</issue><spage>790</spage><epage>792</epage><pages>790-792</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi 2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT's reliability due to the absent of NiSi 2 at the edges and the large effective channel length and width.</abstract><pub>IEEE</pub><doi>10.1109/LED.2015.2438871</doi><tpages>3</tpages></addata></record> |
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| subjects | Contamination Geometry Logic gates Metal-induced lateral crystallization (MILC) polysilicon thin-film transistors Reliability short-channel effect Stress Thin film transistors |
| title | Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation |
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