Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (V th ) region, where the supply voltage (V DD ) is slightly higher than V th . When V DD is scaled down to near V th , the drain current becomes greatly sensitiv...

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Veröffentlicht in:	IEEE transactions on electron devices 2015-06, Vol.62 (6), p.1754-1759
Hauptverfasser:	Hanwool Jeong, Younghwi Yang, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit synthesis CMOS integrated circuits Delays Energy consumption Energy-delay product (EDP) figure of merit (FOM) Inverters near-threshold-voltage circuit design System-on-chip Transistors
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