Machine learning-based VLSI cells shape function estimation
We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the com...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1998-07, Vol.17 (7), p.613-623 |
|---|---|
| Hauptverfasser: | , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 623 |
|---|---|
| container_issue | 7 |
| container_start_page | 613 |
| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 17 |
| creator | Xiao Quan Li Jabri, M.A. |
| description | We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available. |
| doi_str_mv | 10.1109/43.709400 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_709400</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>709400</ieee_id><sourcerecordid>26644586</sourcerecordid><originalsourceid>FETCH-LOGICAL-c266t-6b0102cf5cd8a47a6c7398876e4910aeb2b61fa8f2dce18c28308ac3998505cb3</originalsourceid><addsrcrecordid>eNo9kL1PwzAQxS0EEqUwsDJlQEgMKeePxLaYUMVHpSIGPtbo4p5pUOqUuB3473GVqtOddL977-kxdslhwjnYOyUnGqwCOGIjbqXOFS_4MRuB0CYH0HDKzmL8AeCqEHbE7l_RLZtAWUvYhyZ85zVGWmRf8_dZ5qhtYxaXuKbMb4PbNF3IKG6aFe7Wc3bisY10sZ9j9vn0-DF9yedvz7Ppwzx3oiw3eVkDB-F84RYGlcbSaWmN0SUpywGpFnXJPRovFo64ccJIMOiktaaAwtVyzG4G3XXf_W6Tf7Vq4i4bBuq2sUouShWmTODtALq-i7EnX637lLX_qzhUu3oqJauhnsRe70UxOmx9j8E18fAgkj3XKmFXA9YQ0eG61_gHwJVrLA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26644586</pqid></control><display><type>article</type><title>Machine learning-based VLSI cells shape function estimation</title><source>IEEE Electronic Library (IEL)</source><creator>Xiao Quan Li ; Jabri, M.A.</creator><creatorcontrib>Xiao Quan Li ; Jabri, M.A.</creatorcontrib><description>We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.709400</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit testing ; Delay estimation ; Design. Technologies. Operation analysis. Testing ; Electric, optical and optoelectronic circuits ; Electronics ; Exact sciences and technology ; Integrated circuit layout ; Integrated circuits ; Inverters ; Machine learning ; MOS devices ; Neural networks ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Shape ; Signal generators ; Very large scale integration</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 1998-07, Vol.17 (7), p.613-623</ispartof><rights>1998 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c266t-6b0102cf5cd8a47a6c7398876e4910aeb2b61fa8f2dce18c28308ac3998505cb3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/709400$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/709400$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=2399174$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Xiao Quan Li</creatorcontrib><creatorcontrib>Jabri, M.A.</creatorcontrib><title>Machine learning-based VLSI cells shape function estimation</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available.</description><subject>Applied sciences</subject><subject>Circuit testing</subject><subject>Delay estimation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuit layout</subject><subject>Integrated circuits</subject><subject>Inverters</subject><subject>Machine learning</subject><subject>MOS devices</subject><subject>Neural networks</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Shape</subject><subject>Signal generators</subject><subject>Very large scale integration</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kL1PwzAQxS0EEqUwsDJlQEgMKeePxLaYUMVHpSIGPtbo4p5pUOqUuB3473GVqtOddL977-kxdslhwjnYOyUnGqwCOGIjbqXOFS_4MRuB0CYH0HDKzmL8AeCqEHbE7l_RLZtAWUvYhyZ85zVGWmRf8_dZ5qhtYxaXuKbMb4PbNF3IKG6aFe7Wc3bisY10sZ9j9vn0-DF9yedvz7Ppwzx3oiw3eVkDB-F84RYGlcbSaWmN0SUpywGpFnXJPRovFo64ccJIMOiktaaAwtVyzG4G3XXf_W6Tf7Vq4i4bBuq2sUouShWmTODtALq-i7EnX637lLX_qzhUu3oqJauhnsRe70UxOmx9j8E18fAgkj3XKmFXA9YQ0eG61_gHwJVrLA</recordid><startdate>19980701</startdate><enddate>19980701</enddate><creator>Xiao Quan Li</creator><creator>Jabri, M.A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19980701</creationdate><title>Machine learning-based VLSI cells shape function estimation</title><author>Xiao Quan Li ; Jabri, M.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c266t-6b0102cf5cd8a47a6c7398876e4910aeb2b61fa8f2dce18c28308ac3998505cb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Applied sciences</topic><topic>Circuit testing</topic><topic>Delay estimation</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuit layout</topic><topic>Integrated circuits</topic><topic>Inverters</topic><topic>Machine learning</topic><topic>MOS devices</topic><topic>Neural networks</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Shape</topic><topic>Signal generators</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xiao Quan Li</creatorcontrib><creatorcontrib>Jabri, M.A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xiao Quan Li</au><au>Jabri, M.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Machine learning-based VLSI cells shape function estimation</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1998-07-01</date><risdate>1998</risdate><volume>17</volume><issue>7</issue><spage>613</spage><epage>623</epage><pages>613-623</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.709400</doi><tpages>11</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1998-07, Vol.17 (7), p.613-623 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_ieee_primary_709400 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit testing Delay estimation Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronics Exact sciences and technology Integrated circuit layout Integrated circuits Inverters Machine learning MOS devices Neural networks Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shape Signal generators Very large scale integration |
| title | Machine learning-based VLSI cells shape function estimation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T07%3A13%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Machine%20learning-based%20VLSI%20cells%20shape%20function%20estimation&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Xiao%20Quan%20Li&rft.date=1998-07-01&rft.volume=17&rft.issue=7&rft.spage=613&rft.epage=623&rft.pages=613-623&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/43.709400&rft_dat=%3Cproquest_RIE%3E26644586%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26644586&rft_id=info:pmid/&rft_ieee_id=709400&rfr_iscdi=true |