Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs

Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs

WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in s...

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Hauptverfasser: Gambino, J.P., Weybright, M., Faltermeier, J., Domenicucci, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit stability
Etching
Microstructure
Oxidation
Random access memory
Rapid thermal annealing
Scanning electron microscopy
Silicides
Temperature
Thermal stability
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Weybright, M.
Faltermeier, J.
Domenicucci, A.
description WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in sheet resistance. Enhanced low temperature oxidation of the WSi/sub 2/ results in oxide protrusions along the gate stack sidewalls, and can cause wordline-to-bitline leakage and open bitline contacts in a self-aligned contact process. Agglomeration and oxide protrusions can be minimized by using appropriate anneal conditions.
doi_str_mv 10.1109/IITC.1998.704916
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_704916</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>704916</ieee_id><sourcerecordid>704916</sourcerecordid><originalsourceid>FETCH-ieee_primary_7049163</originalsourceid><addsrcrecordid>eNp9jrsOgjAYRpsYE2_sxul_AaGlIO1owAuDi5I4koIl1pRA2jLw9pro7Lec4ZzhQ2hNsE8I5kGeF6lPOGd-giNOdhO0wAnDNApZHM6QZ-0Lf0Z5TCmbo6x4StMKDdaJSmnlRugauN9UYIcKwgD6To-1eshPYIbaDUZaaDoDBE6VcpBd9xe7QtNGaCu9H5doczwU6XmrpJRlb1QrzFh-_9C_8g2byTg5</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Gambino, J.P. ; Weybright, M. ; Faltermeier, J. ; Domenicucci, A.</creator><creatorcontrib>Gambino, J.P. ; Weybright, M. ; Faltermeier, J. ; Domenicucci, A.</creatorcontrib><description>WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in sheet resistance. Enhanced low temperature oxidation of the WSi/sub 2/ results in oxide protrusions along the gate stack sidewalls, and can cause wordline-to-bitline leakage and open bitline contacts in a self-aligned contact process. Agglomeration and oxide protrusions can be minimized by using appropriate anneal conditions.</description><identifier>ISBN: 0780342852</identifier><identifier>ISBN: 9780780342859</identifier><identifier>DOI: 10.1109/IITC.1998.704916</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit stability ; Etching ; Microstructure ; Oxidation ; Random access memory ; Rapid thermal annealing ; Scanning electron microscopy ; Silicides ; Temperature ; Thermal stability</subject><ispartof>Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102), 1998, p.259-261</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/704916$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,781,785,790,791,2059,4051,4052,27930,54925</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/704916$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gambino, J.P.</creatorcontrib><creatorcontrib>Weybright, M.</creatorcontrib><creatorcontrib>Faltermeier, J.</creatorcontrib><creatorcontrib>Domenicucci, A.</creatorcontrib><title>Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs</title><title>Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)</title><addtitle>IITC</addtitle><description>WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in sheet resistance. Enhanced low temperature oxidation of the WSi/sub 2/ results in oxide protrusions along the gate stack sidewalls, and can cause wordline-to-bitline leakage and open bitline contacts in a self-aligned contact process. Agglomeration and oxide protrusions can be minimized by using appropriate anneal conditions.</description><subject>Circuit stability</subject><subject>Etching</subject><subject>Microstructure</subject><subject>Oxidation</subject><subject>Random access memory</subject><subject>Rapid thermal annealing</subject><subject>Scanning electron microscopy</subject><subject>Silicides</subject><subject>Temperature</subject><subject>Thermal stability</subject><isbn>0780342852</isbn><isbn>9780780342859</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jrsOgjAYRpsYE2_sxul_AaGlIO1owAuDi5I4koIl1pRA2jLw9pro7Lec4ZzhQ2hNsE8I5kGeF6lPOGd-giNOdhO0wAnDNApZHM6QZ-0Lf0Z5TCmbo6x4StMKDdaJSmnlRugauN9UYIcKwgD6To-1eshPYIbaDUZaaDoDBE6VcpBd9xe7QtNGaCu9H5doczwU6XmrpJRlb1QrzFh-_9C_8g2byTg5</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Gambino, J.P.</creator><creator>Weybright, M.</creator><creator>Faltermeier, J.</creator><creator>Domenicucci, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1998</creationdate><title>Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs</title><author>Gambino, J.P. ; Weybright, M. ; Faltermeier, J. ; Domenicucci, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7049163</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Circuit stability</topic><topic>Etching</topic><topic>Microstructure</topic><topic>Oxidation</topic><topic>Random access memory</topic><topic>Rapid thermal annealing</topic><topic>Scanning electron microscopy</topic><topic>Silicides</topic><topic>Temperature</topic><topic>Thermal stability</topic><toplevel>online_resources</toplevel><creatorcontrib>Gambino, J.P.</creatorcontrib><creatorcontrib>Weybright, M.</creatorcontrib><creatorcontrib>Faltermeier, J.</creatorcontrib><creatorcontrib>Domenicucci, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gambino, J.P.</au><au>Weybright, M.</au><au>Faltermeier, J.</au><au>Domenicucci, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs</atitle><btitle>Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)</btitle><stitle>IITC</stitle><date>1998</date><risdate>1998</risdate><spage>259</spage><epage>261</epage><pages>259-261</pages><isbn>0780342852</isbn><isbn>9780780342859</isbn><abstract>WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in sheet resistance. Enhanced low temperature oxidation of the WSi/sub 2/ results in oxide protrusions along the gate stack sidewalls, and can cause wordline-to-bitline leakage and open bitline contacts in a self-aligned contact process. Agglomeration and oxide protrusions can be minimized by using appropriate anneal conditions.</abstract><pub>IEEE</pub><doi>10.1109/IITC.1998.704916</doi></addata></record>
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subjects Circuit stability
Etching
Microstructure
Oxidation
Random access memory
Rapid thermal annealing
Scanning electron microscopy
Silicides
Temperature
Thermal stability
title Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-11T14%3A34%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Thermal%20stability%20of%20WSi/sub%202/%20polycide%20structures%20for%201%20Gbit%20DRAMs&rft.btitle=Proceedings%20of%20the%20IEEE%201998%20International%20Interconnect%20Technology%20Conference%20(Cat.%20No.98EX102)&rft.au=Gambino,%20J.P.&rft.date=1998&rft.spage=259&rft.epage=261&rft.pages=259-261&rft.isbn=0780342852&rft.isbn_list=9780780342859&rft_id=info:doi/10.1109/IITC.1998.704916&rft_dat=%3Cieee_6IE%3E704916%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=704916&rfr_iscdi=true