A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Hardware-based computer vision accelerators will be an essential part of future mobile devices to meet the low power and real-time processing requirement. To realize a high energy efficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to vision proces...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2015-04, Vol.50 (4), p.1070-1079
Hauptverfasser:	Knag, Phil, Jung Kuk Kim, Chen, Thomas, Zhengya Zhang
Format:	Artikel
Sprache:	eng
Schlagworte:	Application specific integrated circuits Encoding Feature extraction hardware acceleration Image coding Image reconstruction Inference algorithms neural network architecture Neurons sparse and independent local network sparse coding
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