Error-Correcting Code Aware Memory Subsystem
An error-correcting code (ECC) immune to bit errors has been widely used in reliable computer systems. However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynami...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2014-11, Vol.33 (11), p.1706-1717 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Jang, Wooyoung |
| description | An error-correcting code (ECC) immune to bit errors has been widely used in reliable computer systems. However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. Moreover, the ECC-aware memory subsystem improves up to 2.5 times higher memory performance on synthetic benchmarks. |
| doi_str_mv | 10.1109/TCAD.2014.2351494 |
| format | Article |
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However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. 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However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. 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However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2014-11, Vol.33 (11), p.1706-1717 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Buffer storage Clocks Computer aided design Computers Design engineering Dynamical systems Dynamics Error correction Error correction codes Memory management Microprocessors Multimedia Optimization Random access memory Reliability SDRAM Synchronous |
| title | Error-Correcting Code Aware Memory Subsystem |
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