Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2015-09, Vol.23 (9), p.1689-1699
Hauptverfasser: Kim, Eun Ji, Lee, Jea Hack, Sunwoo, Myung Hoon
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description This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages.
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subjects Computer architecture
Delays
Discrete Fourier transforms
Fast Fourier transform (FFT)
Hardware
mixed-radix multipath delay commutator (MRMDC)
OFDM
optical orthogonal frequency-division multiplexing (O-OFDM)
Program processors
Throughput
ultrawideband (UWB)
wireless personal area network (WPAN)
title Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors
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