Verification of Transactional Memory in POWER8
Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operati...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 6 |
|---|---|
| container_issue | |
| container_start_page | 1 |
| container_title | |
| container_volume | |
| creator | Adir, Allon Goodman, Dave Hershcovich, Daniel Hershkovitz, Oz Hickerson, Bryan Holtz, Karen Kadry, Wisam Koyfman, Anatoly Ludden, John Meissner, Charles Nahir, Amir Pratt, Randall R. Schiffli, Mike St. Onge, Brett Thompto, Brian Tsanko, Elena Ziv, Avi |
| description | Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core. |
| doi_str_mv | 10.1145/2593069.2593241 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>acm_RIE</sourceid><recordid>TN_cdi_ieee_primary_6881385</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6881385</ieee_id><sourcerecordid>acm_books_10_1145_2593069_2593241</sourcerecordid><originalsourceid>FETCH-LOGICAL-a247t-91685d74ae5dce50cca31f8eddeeb4ff3f51527b1b9937a093ab7594335df7e53</originalsourceid><addsrcrecordid>eNqNkDtPw0AQhA8BEiGkpqBxSWOz673znUsUhYcUFITCozud7T3pILaRnSb_HlvxD6Aazc5otPqEuEZIEKW6S1VOkOXJqKnEE3GJUufDDXV6OhoFlGoCOhMz0GRiBPi6EIu-_wYAJIlDeyaSD-6CD6Xbh7aJWh9tO9f0rhyt20UvXLfdIQpN9Lr5XL2ZK3Hu3a7nxaRz8f6w2i6f4vXm8Xl5v45dKvU-zjEzqtLSsapKVlCWjtAbrirmQnpPXqFKdYHF8LF2kJMrtMolkaq8ZkVzcXPcDcxsf7tQu-5gM2OQzJjeHlNX1rZo25_eItgRi52w2AnLUE3-WbVFF9jTHz_PXPo</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Verification of Transactional Memory in POWER8</title><source>IEEE Electronic Library (IEL)</source><creator>Adir, Allon ; Goodman, Dave ; Hershcovich, Daniel ; Hershkovitz, Oz ; Hickerson, Bryan ; Holtz, Karen ; Kadry, Wisam ; Koyfman, Anatoly ; Ludden, John ; Meissner, Charles ; Nahir, Amir ; Pratt, Randall R. ; Schiffli, Mike ; St. Onge, Brett ; Thompto, Brian ; Tsanko, Elena ; Ziv, Avi</creator><creatorcontrib>Adir, Allon ; Goodman, Dave ; Hershcovich, Daniel ; Hershkovitz, Oz ; Hickerson, Bryan ; Holtz, Karen ; Kadry, Wisam ; Koyfman, Anatoly ; Ludden, John ; Meissner, Charles ; Nahir, Amir ; Pratt, Randall R. ; Schiffli, Mike ; St. Onge, Brett ; Thompto, Brian ; Tsanko, Elena ; Ziv, Avi</creatorcontrib><description>Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 1450327303</identifier><identifier>ISBN: 9781450327305</identifier><identifier>EISBN: 1479930172</identifier><identifier>EISBN: 9781479930173</identifier><identifier>DOI: 10.1145/2593069.2593241</identifier><language>eng</language><publisher>New York, NY, USA: ACM</publisher><subject>Computer architecture ; Generators ; Hardware ; Hardware -- Hardware validation ; Hardware -- Hardware validation -- Functional verification ; Instruction sets ; Registers ; Transient analysis</subject><ispartof>2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6</ispartof><rights>2014 ACM</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6881385$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,796,23930,23931,25140,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6881385$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Adir, Allon</creatorcontrib><creatorcontrib>Goodman, Dave</creatorcontrib><creatorcontrib>Hershcovich, Daniel</creatorcontrib><creatorcontrib>Hershkovitz, Oz</creatorcontrib><creatorcontrib>Hickerson, Bryan</creatorcontrib><creatorcontrib>Holtz, Karen</creatorcontrib><creatorcontrib>Kadry, Wisam</creatorcontrib><creatorcontrib>Koyfman, Anatoly</creatorcontrib><creatorcontrib>Ludden, John</creatorcontrib><creatorcontrib>Meissner, Charles</creatorcontrib><creatorcontrib>Nahir, Amir</creatorcontrib><creatorcontrib>Pratt, Randall R.</creatorcontrib><creatorcontrib>Schiffli, Mike</creatorcontrib><creatorcontrib>St. Onge, Brett</creatorcontrib><creatorcontrib>Thompto, Brian</creatorcontrib><creatorcontrib>Tsanko, Elena</creatorcontrib><creatorcontrib>Ziv, Avi</creatorcontrib><title>Verification of Transactional Memory in POWER8</title><title>2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)</title><addtitle>DAC</addtitle><description>Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.</description><subject>Computer architecture</subject><subject>Generators</subject><subject>Hardware</subject><subject>Hardware -- Hardware validation</subject><subject>Hardware -- Hardware validation -- Functional verification</subject><subject>Instruction sets</subject><subject>Registers</subject><subject>Transient analysis</subject><issn>0738-100X</issn><isbn>1450327303</isbn><isbn>9781450327305</isbn><isbn>1479930172</isbn><isbn>9781479930173</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2014</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDtPw0AQhA8BEiGkpqBxSWOz673znUsUhYcUFITCozud7T3pILaRnSb_HlvxD6Aazc5otPqEuEZIEKW6S1VOkOXJqKnEE3GJUufDDXV6OhoFlGoCOhMz0GRiBPi6EIu-_wYAJIlDeyaSD-6CD6Xbh7aJWh9tO9f0rhyt20UvXLfdIQpN9Lr5XL2ZK3Hu3a7nxaRz8f6w2i6f4vXm8Xl5v45dKvU-zjEzqtLSsapKVlCWjtAbrirmQnpPXqFKdYHF8LF2kJMrtMolkaq8ZkVzcXPcDcxsf7tQu-5gM2OQzJjeHlNX1rZo25_eItgRi52w2AnLUE3-WbVFF9jTHz_PXPo</recordid><startdate>20140601</startdate><enddate>20140601</enddate><creator>Adir, Allon</creator><creator>Goodman, Dave</creator><creator>Hershcovich, Daniel</creator><creator>Hershkovitz, Oz</creator><creator>Hickerson, Bryan</creator><creator>Holtz, Karen</creator><creator>Kadry, Wisam</creator><creator>Koyfman, Anatoly</creator><creator>Ludden, John</creator><creator>Meissner, Charles</creator><creator>Nahir, Amir</creator><creator>Pratt, Randall R.</creator><creator>Schiffli, Mike</creator><creator>St. Onge, Brett</creator><creator>Thompto, Brian</creator><creator>Tsanko, Elena</creator><creator>Ziv, Avi</creator><general>ACM</general><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20140601</creationdate><title>Verification of Transactional Memory in POWER8</title><author>Adir, Allon ; Goodman, Dave ; Hershcovich, Daniel ; Hershkovitz, Oz ; Hickerson, Bryan ; Holtz, Karen ; Kadry, Wisam ; Koyfman, Anatoly ; Ludden, John ; Meissner, Charles ; Nahir, Amir ; Pratt, Randall R. ; Schiffli, Mike ; St. Onge, Brett ; Thompto, Brian ; Tsanko, Elena ; Ziv, Avi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a247t-91685d74ae5dce50cca31f8eddeeb4ff3f51527b1b9937a093ab7594335df7e53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Computer architecture</topic><topic>Generators</topic><topic>Hardware</topic><topic>Hardware -- Hardware validation</topic><topic>Hardware -- Hardware validation -- Functional verification</topic><topic>Instruction sets</topic><topic>Registers</topic><topic>Transient analysis</topic><toplevel>online_resources</toplevel><creatorcontrib>Adir, Allon</creatorcontrib><creatorcontrib>Goodman, Dave</creatorcontrib><creatorcontrib>Hershcovich, Daniel</creatorcontrib><creatorcontrib>Hershkovitz, Oz</creatorcontrib><creatorcontrib>Hickerson, Bryan</creatorcontrib><creatorcontrib>Holtz, Karen</creatorcontrib><creatorcontrib>Kadry, Wisam</creatorcontrib><creatorcontrib>Koyfman, Anatoly</creatorcontrib><creatorcontrib>Ludden, John</creatorcontrib><creatorcontrib>Meissner, Charles</creatorcontrib><creatorcontrib>Nahir, Amir</creatorcontrib><creatorcontrib>Pratt, Randall R.</creatorcontrib><creatorcontrib>Schiffli, Mike</creatorcontrib><creatorcontrib>St. Onge, Brett</creatorcontrib><creatorcontrib>Thompto, Brian</creatorcontrib><creatorcontrib>Tsanko, Elena</creatorcontrib><creatorcontrib>Ziv, Avi</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Adir, Allon</au><au>Goodman, Dave</au><au>Hershcovich, Daniel</au><au>Hershkovitz, Oz</au><au>Hickerson, Bryan</au><au>Holtz, Karen</au><au>Kadry, Wisam</au><au>Koyfman, Anatoly</au><au>Ludden, John</au><au>Meissner, Charles</au><au>Nahir, Amir</au><au>Pratt, Randall R.</au><au>Schiffli, Mike</au><au>St. Onge, Brett</au><au>Thompto, Brian</au><au>Tsanko, Elena</au><au>Ziv, Avi</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Verification of Transactional Memory in POWER8</atitle><btitle>2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)</btitle><stitle>DAC</stitle><date>2014-06-01</date><risdate>2014</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>0738-100X</issn><isbn>1450327303</isbn><isbn>9781450327305</isbn><eisbn>1479930172</eisbn><eisbn>9781479930173</eisbn><abstract>Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/2593069.2593241</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0738-100X |
| ispartof | 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_ieee_primary_6881385 |
| source | IEEE Electronic Library (IEL) |
| subjects | Computer architecture Generators Hardware Hardware -- Hardware validation Hardware -- Hardware validation -- Functional verification Instruction sets Registers Transient analysis |
| title | Verification of Transactional Memory in POWER8 |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T19%3A32%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-acm_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Verification%20of%20Transactional%20Memory%20in%20POWER8&rft.btitle=2014%2051st%20ACM/EDAC/IEEE%20Design%20Automation%20Conference%20(DAC)&rft.au=Adir,%20Allon&rft.date=2014-06-01&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.issn=0738-100X&rft.isbn=1450327303&rft.isbn_list=9781450327305&rft_id=info:doi/10.1145/2593069.2593241&rft_dat=%3Cacm_RIE%3Eacm_books_10_1145_2593069_2593241%3C/acm_RIE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1479930172&rft.eisbn_list=9781479930173&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6881385&rfr_iscdi=true |