Implementation of a 6n \pm 1 Repetitive Controller Subject to Fractional Delays

Repetitive schemes represent an attractive solution for harmonic compensation, as they are easy to implement and require a reduced computational effort. Repetitive schemes involve the interconnection of delay lines usually implemented in digital form. A delay line is realized digitally by reserving a given number of memory localities, where samples are allocated and released after a specific number of sampling periods (discrete delay) equivalent to the delay time. Such a discrete delay computed as the ratio between the required delay time and the sampling period must be an integer number in the best scenario. However, the discrete delay may have a fractional part due to limitations on the sampling period or the required delay time. This issue is referred in signal processing literature as fractional delay (FD). This paper presents a solution to implement repetitive schemes subject to such an FD issue. The solution consists in the introduction, on each delay line, of an additional filter aimed to compensate such an FD. In particular, this paper focuses on a repetitive scheme that is able to compensate harmonics 6n ±1. Experimental results are presented to confirm the benefits of the proposed scheme.