A Digital Frequency Multiplication Technique for Energy Efficient Transmitters
A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicro...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2015-04, Vol.23 (4), p.781-785 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Manikandan, R. R. Kumar, Abhishek Amrutur, Bharadwaj |
| description | A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-μm CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations. |
| doi_str_mv | 10.1109/TVLSI.2014.2315232 |
| format | Article |
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The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.</description><subject>Amplitude shift keying</subject><subject>Binary frequency-shift-keying (BFSK) transmitter (TX)</subject><subject>class-D power amplifier (PA)</subject><subject>energy efficient</subject><subject>Frequency conversion</subject><subject>frequency multiplication technique</subject><subject>Frequency synthesizers</subject><subject>Logic gates</subject><subject>Phase locked loops</subject><subject>Transistors</subject><subject>Voltage-controlled oscillators</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM9OwzAMhyMEEmPwAnDJC3Q4_5r2OI1tTBpwoHCt2tQZQV03kuzQt6djE77Y0s-fZX2E3DOYMAb5Y_G5fl9NODA54YIpLvgFGTGldJIPdTnMkIok4wyuyU0I3zBsyhxG5HVKn9zGxaqlC48_B-xMT18ObXT71pkqul1HCzRfnRsyaneezjv0m57OrXXGYRdp4asubF2M6MMtubJVG_Du3MfkYzEvZs_J-m25mk3XiZGgYyJ5qozhHGSjNNY5a0RdDy-xxkJmM2tUowBRI0NhVKpVrVOta2sBBGrGxJjw013jdyF4tOXeu23l-5JBeTRS_hkpj0bKs5EBejhBDhH_gTQDLoUUv0uMXfU</recordid><startdate>20150401</startdate><enddate>20150401</enddate><creator>Manikandan, R. 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R.</creatorcontrib><creatorcontrib>Kumar, Abhishek</creatorcontrib><creatorcontrib>Amrutur, Bharadwaj</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Manikandan, R. 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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2015-04, Vol.23 (4), p.781-785 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Amplitude shift keying Binary frequency-shift-keying (BFSK) transmitter (TX) class-D power amplifier (PA) energy efficient Frequency conversion frequency multiplication technique Frequency synthesizers Logic gates Phase locked loops Transistors Voltage-controlled oscillators |
| title | A Digital Frequency Multiplication Technique for Energy Efficient Transmitters |
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