Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors
We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation lea...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 2014-05, Vol.61 (5), p.1583-1589 |
|---|---|
| Hauptverfasser: | , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1589 |
|---|---|
| container_issue | 5 |
| container_start_page | 1583 |
| container_title | IEEE transactions on electron devices |
| container_volume | 61 |
| creator | Carrion, Enrique A. Serov, Andrey Y. Islam, Sharnali Behnam, Ashkan Malik, Akshay Feng Xiong Bianchi, Massimiliano Sordan, Roman Pop, Eric |
| description | We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm -2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology. |
| doi_str_mv | 10.1109/TED.2014.2309651 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_6783736</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6783736</ieee_id><sourcerecordid>3377124391</sourcerecordid><originalsourceid>FETCH-LOGICAL-c432t-8ac66c7601c8acca83c626d4a8843d7cef17832a69194ecd819338fb565cce8d3</originalsourceid><addsrcrecordid>eNpdkDFPwzAQRi0EEqWwI7FEYmFJsWPHsUdU2oJUAUOYLXO5qKnSONjJUH49rloxMN2d9L5Pp0fILaMzxqh-LBfPs4wyMcs41TJnZ2TC8rxItRTynEwoZSrVXPFLchXCNp5SiGxCzMs-DOgxNCFdesTkzXYuILiuSj7GNmCVLFqEwTdg22S-sd5C5JsfOzSuS1ydlK5PV3aI4MrbfoMdJqW3XSwcnA_X5KK2sebmNKfkc7ko5y_p-n31On9apyB4NqTKgpRQSMogrmAVB5nJSlilBK8KwJoVimdWaqYFQqWY5lzVX7nMAVBVfEoejr29d98jhsHsmgDYtrZDNwbDZJRDuRA6ovf_0K0bfRe_MywXudJUKBkpeqTAuxA81qb3zc76vWHUHIybaNwcjJuT8Ri5O0YaRPzDZXy84JL_ApwGfMQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1545890486</pqid></control><display><type>article</type><title>Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors</title><source>IEEE Electronic Library (IEL)</source><creator>Carrion, Enrique A. ; Serov, Andrey Y. ; Islam, Sharnali ; Behnam, Ashkan ; Malik, Akshay ; Feng Xiong ; Bianchi, Massimiliano ; Sordan, Roman ; Pop, Eric</creator><creatorcontrib>Carrion, Enrique A. ; Serov, Andrey Y. ; Islam, Sharnali ; Behnam, Ashkan ; Malik, Akshay ; Feng Xiong ; Bianchi, Massimiliano ; Sordan, Roman ; Pop, Eric</creatorcontrib><description>We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm -2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2014.2309651</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Charge ; Charge carrier processes ; Charge trapping ; Defects ; Dielectrics ; Drains ; field-effect transistors (FETs) ; Gates ; Graphene ; high-κ dielectric ; Hysteresis ; Logic gates ; mobility ; nanosecond pulsed measurements ; Nanostructure ; Pulse measurements ; Trapping ; Voltage measurement</subject><ispartof>IEEE transactions on electron devices, 2014-05, Vol.61 (5), p.1583-1589</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) May 2014</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c432t-8ac66c7601c8acca83c626d4a8843d7cef17832a69194ecd819338fb565cce8d3</citedby><cites>FETCH-LOGICAL-c432t-8ac66c7601c8acca83c626d4a8843d7cef17832a69194ecd819338fb565cce8d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6783736$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,782,786,798,27933,27934,54767</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6783736$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Carrion, Enrique A.</creatorcontrib><creatorcontrib>Serov, Andrey Y.</creatorcontrib><creatorcontrib>Islam, Sharnali</creatorcontrib><creatorcontrib>Behnam, Ashkan</creatorcontrib><creatorcontrib>Malik, Akshay</creatorcontrib><creatorcontrib>Feng Xiong</creatorcontrib><creatorcontrib>Bianchi, Massimiliano</creatorcontrib><creatorcontrib>Sordan, Roman</creatorcontrib><creatorcontrib>Pop, Eric</creatorcontrib><title>Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm -2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.</description><subject>Charge</subject><subject>Charge carrier processes</subject><subject>Charge trapping</subject><subject>Defects</subject><subject>Dielectrics</subject><subject>Drains</subject><subject>field-effect transistors (FETs)</subject><subject>Gates</subject><subject>Graphene</subject><subject>high-κ dielectric</subject><subject>Hysteresis</subject><subject>Logic gates</subject><subject>mobility</subject><subject>nanosecond pulsed measurements</subject><subject>Nanostructure</subject><subject>Pulse measurements</subject><subject>Trapping</subject><subject>Voltage measurement</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkDFPwzAQRi0EEqWwI7FEYmFJsWPHsUdU2oJUAUOYLXO5qKnSONjJUH49rloxMN2d9L5Pp0fILaMzxqh-LBfPs4wyMcs41TJnZ2TC8rxItRTynEwoZSrVXPFLchXCNp5SiGxCzMs-DOgxNCFdesTkzXYuILiuSj7GNmCVLFqEwTdg22S-sd5C5JsfOzSuS1ydlK5PV3aI4MrbfoMdJqW3XSwcnA_X5KK2sebmNKfkc7ko5y_p-n31On9apyB4NqTKgpRQSMogrmAVB5nJSlilBK8KwJoVimdWaqYFQqWY5lzVX7nMAVBVfEoejr29d98jhsHsmgDYtrZDNwbDZJRDuRA6ovf_0K0bfRe_MywXudJUKBkpeqTAuxA81qb3zc76vWHUHIybaNwcjJuT8Ri5O0YaRPzDZXy84JL_ApwGfMQ</recordid><startdate>20140501</startdate><enddate>20140501</enddate><creator>Carrion, Enrique A.</creator><creator>Serov, Andrey Y.</creator><creator>Islam, Sharnali</creator><creator>Behnam, Ashkan</creator><creator>Malik, Akshay</creator><creator>Feng Xiong</creator><creator>Bianchi, Massimiliano</creator><creator>Sordan, Roman</creator><creator>Pop, Eric</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7QF</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope><scope>JG9</scope></search><sort><creationdate>20140501</creationdate><title>Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors</title><author>Carrion, Enrique A. ; Serov, Andrey Y. ; Islam, Sharnali ; Behnam, Ashkan ; Malik, Akshay ; Feng Xiong ; Bianchi, Massimiliano ; Sordan, Roman ; Pop, Eric</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c432t-8ac66c7601c8acca83c626d4a8843d7cef17832a69194ecd819338fb565cce8d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Charge</topic><topic>Charge carrier processes</topic><topic>Charge trapping</topic><topic>Defects</topic><topic>Dielectrics</topic><topic>Drains</topic><topic>field-effect transistors (FETs)</topic><topic>Gates</topic><topic>Graphene</topic><topic>high-κ dielectric</topic><topic>Hysteresis</topic><topic>Logic gates</topic><topic>mobility</topic><topic>nanosecond pulsed measurements</topic><topic>Nanostructure</topic><topic>Pulse measurements</topic><topic>Trapping</topic><topic>Voltage measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Carrion, Enrique A.</creatorcontrib><creatorcontrib>Serov, Andrey Y.</creatorcontrib><creatorcontrib>Islam, Sharnali</creatorcontrib><creatorcontrib>Behnam, Ashkan</creatorcontrib><creatorcontrib>Malik, Akshay</creatorcontrib><creatorcontrib>Feng Xiong</creatorcontrib><creatorcontrib>Bianchi, Massimiliano</creatorcontrib><creatorcontrib>Sordan, Roman</creatorcontrib><creatorcontrib>Pop, Eric</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Aluminium Industry Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Materials Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Carrion, Enrique A.</au><au>Serov, Andrey Y.</au><au>Islam, Sharnali</au><au>Behnam, Ashkan</au><au>Malik, Akshay</au><au>Feng Xiong</au><au>Bianchi, Massimiliano</au><au>Sordan, Roman</au><au>Pop, Eric</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2014-05-01</date><risdate>2014</risdate><volume>61</volume><issue>5</issue><spage>1583</spage><epage>1589</epage><pages>1583-1589</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>We measure top-gated graphene field-effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases by ~10% over timescales of ~10 μs, consistent with charge trapping mechanisms. The pulsed operation leads to hysteresis-free I-V characteristics that are studied with pulses as short as 75 and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple dc characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/μm. In addition, using modeling and capacitance-voltage measurements, we extract trap densities up to 1012 cm -2 in the top-gate dielectric (here Al 2 O 3 ). This study illustrates important timeand field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2014.2309651</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 2014-05, Vol.61 (5), p.1583-1589 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_ieee_primary_6783736 |
| source | IEEE Electronic Library (IEL) |
| subjects | Charge Charge carrier processes Charge trapping Defects Dielectrics Drains field-effect transistors (FETs) Gates Graphene high-κ dielectric Hysteresis Logic gates mobility nanosecond pulsed measurements Nanostructure Pulse measurements Trapping Voltage measurement |
| title | Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-01T05%3A30%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Hysteresis-Free%20Nanosecond%20Pulsed%20Electrical%20Characterization%20of%20Top-Gated%20Graphene%20Transistors&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Carrion,%20Enrique%20A.&rft.date=2014-05-01&rft.volume=61&rft.issue=5&rft.spage=1583&rft.epage=1589&rft.pages=1583-1589&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2014.2309651&rft_dat=%3Cproquest_RIE%3E3377124391%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1545890486&rft_id=info:pmid/&rft_ieee_id=6783736&rfr_iscdi=true |