A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2014-08, Vol.61 (8), p.2466-2472
Hauptverfasser:	Lee, Joon-Yeong, Yoon, Jong-Hyeok, Bae, Hyeon-Min
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive control systems Bandwidth Bang-bang PLL Calibration CDR Circuits Clocks CMOS Gain Jitter Kalman filtering Kalman filters Kalman gain Noise Optimization Quantization (signal) serial links serial-in/serial-out Serials
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container_end_page	2472
container_issue	8
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container_title	IEEE transactions on circuits and systems. I, Regular papers
container_volume	61
creator	Lee, Joon-Yeong Yoon, Jong-Hyeok Bae, Hyeon-Min
description	This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10 -13 while consuming 82 mW at 10-Gb/s.
doi_str_mv	10.1109/TCSI.2014.2309861
format	Article
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The testchip recovers clock and data with a bit error rate of less than 10 -13 while consuming 82 mW at 10-Gb/s.</description><subject>Adaptive control systems</subject><subject>Bandwidth</subject><subject>Bang-bang PLL</subject><subject>Calibration</subject><subject>CDR</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Gain</subject><subject>Jitter</subject><subject>Kalman filtering</subject><subject>Kalman filters</subject><subject>Kalman gain</subject><subject>Noise</subject><subject>Optimization</subject><subject>Quantization (signal)</subject><subject>serial links</subject><subject>serial-in/serial-out</subject><subject>Serials</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLxDAQgIsoqKs_QLwEvHjpbibpIzmuVdeFguADjyFNU8zaNmvSKv57U3bx4GGYgflmmPmi6ALwHADzxUvxvJ4TDMmcUMxZBgfRCaQpizHD2eFUJzxmlLDj6NT7DcaEYwonkVgiwPGqWnhU3D6hNzO8I9mjZS23g_nS6DGkbuxQae02vpF9_W3qgBSyNZWTg3WoCfGsnZEtKmzXjb1RcjC2R6XpP_xZdNTI1uvzfZ5Fr_d3L8VDXD6u1sWyjBXl2RDnWNc8JYznioPiDOfhi0pSxTmwKsdZSigheVrXDZCqhqaqFYMmyRpJlNJAZ9H1bu_W2c9R-0F0xivdtrLXdvQiuOA5YAJpQK_-oRs7uj5cJyZLQBKasEDBjlLOeu90I7bOdNL9CMBiUi4m5WJSLvbKw8zlbsZorf_4LGehDfQX4q96kg</recordid><startdate>20140801</startdate><enddate>20140801</enddate><creator>Lee, Joon-Yeong</creator><creator>Yoon, Jong-Hyeok</creator><creator>Bae, Hyeon-Min</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Joon-Yeong</au><au>Yoon, Jong-Hyeok</au><au>Bae, Hyeon-Min</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2014-08-01</date><risdate>2014</risdate><volume>61</volume><issue>8</issue><spage>2466</spage><epage>2472</epage><pages>2466-2472</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10 -13 while consuming 82 mW at 10-Gb/s.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2014.2309861</doi><tpages>7</tpages></addata></record>
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subjects	Adaptive control systems Bandwidth Bang-bang PLL Calibration CDR Circuits Clocks CMOS Gain Jitter Kalman filtering Kalman filters Kalman gain Noise Optimization Quantization (signal) serial links serial-in/serial-out Serials
title	A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links
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