A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs

The recently proposed GPGPU architecture has added a multi-level hierarchy of shared cache to better exploit the data locality of general purpose applications. The GPGPU design philosophy allocates most of the chip area to processing cores, and thus results in a relatively small cache shared by a la...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on computers 2015-04, Vol.64 (4), p.884-898
Hauptverfasser:	Lai, Bo-Cheng Charles, Kuo, Hsien-Kai, Jou, Jing-Yang
Format:	Artikel
Sprache:	eng
Schlagworte:	Arrays cache memories Graphics processing units Instruction sets Kernel Message systems Multithreaded processors Optimization performance analysis and design aids shared memory
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!