An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2014-08, Vol.61 (8), p.2326-2336
Hauptverfasser:	Kim, Yeomyung, Kim, Tae Wook
Format:	Artikel
Sprache:	eng
Schlagworte:	3-D Vernier space Architecture Computer architecture Converters Delay Delays Dynamic range Dynamical systems Error correction High integrated nonlinearity Linearity Nonlinearity Power demand Redundancy redundancy and error correction Three dimensional time-of-flight (ToF) application time-to-digital converter (TDC) zoom-in architecture
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container_title	IEEE transactions on circuits and systems. I, Regular papers
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creator	Kim, Yeomyung Kim, Tae Wook
description	This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13- μm CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ±1.5 LSB, a power consumption of 328.8 μW, and a die area of 0.28 mm 2 .
doi_str_mv	10.1109/TCSI.2014.2304656
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I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, Yeomyung</au><au>Kim, Tae Wook</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2014-08-01</date><risdate>2014</risdate><volume>61</volume><issue>8</issue><spage>2326</spage><epage>2336</epage><pages>2326-2336</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13- μm CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ±1.5 LSB, a power consumption of 328.8 μW, and a die area of 0.28 mm 2 .</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2014.2304656</doi><tpages>11</tpages></addata></record>
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subjects	3-D Vernier space Architecture Computer architecture Converters Delay Delays Dynamic range Dynamical systems Error correction High integrated nonlinearity Linearity Nonlinearity Power demand Redundancy redundancy and error correction Three dimensional time-of-flight (ToF) application time-to-digital converter (TDC) zoom-in architecture
title	An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space
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