A CMOS 6b 400 M sample/s ADC with error correction

Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermome...

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Hauptverfasser: Tsukamoto, S., Endo, T., Schofield, W.G.
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Endo, T.
Schofield, W.G.
description Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.
doi_str_mv 10.1109/ISSCC.1998.672413
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identifier ISSN: 0193-6530
ispartof 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156), 1998, p.152-153
issn 0193-6530
2376-8606
language eng
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Error analysis
Error correction
Frequency measurement
Q measurement
Solid state circuits
Timing
title A CMOS 6b 400 M sample/s ADC with error correction
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