A CMOS 6b 400 M sample/s ADC with error correction
Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermome...
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creator | Tsukamoto, S. Endo, T. Schofield, W.G. |
description | Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection. |
doi_str_mv | 10.1109/ISSCC.1998.672413 |
format | Conference Proceeding |
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This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.</description><subject>Error analysis</subject><subject>Error correction</subject><subject>Frequency measurement</subject><subject>Q measurement</subject><subject>Solid state circuits</subject><subject>Timing</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9780780343443</isbn><isbn>0780343441</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssKwjAQABcfYH18gJ72B9puujFNjhIVPRQP9S5VIlbUSiKIf6-gZ2FgDnMZgLGgRAgy6bosrU2EMTpReSYFtyDKOFexVqTaMDK5pg8sWUruQETCcKymTD3oh3AmoqlROoJshrbYlKj2KImwwFBd7xeXBpzNLT7rxwmd943HQ-O9Ozzq5jaE7rG6BDf6eQCT5WJrV3HtnNvdfX2t_Gv3veK_8Q3QTTRN</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Tsukamoto, S.</creator><creator>Endo, T.</creator><creator>Schofield, W.G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1998</creationdate><title>A CMOS 6b 400 M sample/s ADC with error correction</title><author>Tsukamoto, S. ; Endo, T. ; Schofield, W.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_6724133</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Error analysis</topic><topic>Error correction</topic><topic>Frequency measurement</topic><topic>Q measurement</topic><topic>Solid state circuits</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Tsukamoto, S.</creatorcontrib><creatorcontrib>Endo, T.</creatorcontrib><creatorcontrib>Schofield, W.G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tsukamoto, S.</au><au>Endo, T.</au><au>Schofield, W.G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A CMOS 6b 400 M sample/s ADC with error correction</atitle><btitle>1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)</btitle><stitle>ISSCC</stitle><date>1998</date><risdate>1998</risdate><spage>152</spage><epage>153</epage><pages>152-153</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9780780343443</isbn><isbn>0780343441</isbn><abstract>Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.1998.672413</doi></addata></record> |
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identifier | ISSN: 0193-6530 |
ispartof | 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156), 1998, p.152-153 |
issn | 0193-6530 2376-8606 |
language | eng |
recordid | cdi_ieee_primary_672413 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Error analysis Error correction Frequency measurement Q measurement Solid state circuits Timing |
title | A CMOS 6b 400 M sample/s ADC with error correction |
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