A 28 GHz Hybrid PLL in 32 nm SOI CMOS

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proport...

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Bibliographische Detailangaben

Veröffentlicht in:	IEEE journal of solid-state circuits 2014-04, Vol.49 (4), p.1027-1035
Hauptverfasser:	Ferriss, Mark, Rylyakov, Alexander, Tierno, Jose A., Ainspan, Herschel, Friedman, Daniel J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitors Charge pumps Clocks DPLL frequency synthesizers hybrid PLL Noise phase locked loop Phase locked loops PLL Switches Voltage-controlled oscillators
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