A 28 GHz Hybrid PLL in 32 nm SOI CMOS

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proport...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2014-04, Vol.49 (4), p.1027-1035
Hauptverfasser:	Ferriss, Mark, Rylyakov, Alexander, Tierno, Jose A., Ainspan, Herschel, Friedman, Daniel J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitors Charge pumps Clocks DPLL frequency synthesizers hybrid PLL Noise phase locked loop Phase locked loops PLL Switches Voltage-controlled oscillators
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container_end_page	1035
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container_title	IEEE journal of solid-state circuits
container_volume	49
creator	Ferriss, Mark Rylyakov, Alexander Tierno, Jose A. Ainspan, Herschel Friedman, Daniel J.
description	A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is -110 dBc/Hz at 10 MHz offset. The 14 × 160 μm 2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.
doi_str_mv	10.1109/JSSC.2014.2299273
format	Article
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The 14 × 160 μm 2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.</description><subject>Capacitors</subject><subject>Charge pumps</subject><subject>Clocks</subject><subject>DPLL</subject><subject>frequency synthesizers</subject><subject>hybrid PLL</subject><subject>Noise</subject><subject>phase locked loop</subject><subject>Phase locked loops</subject><subject>PLL</subject><subject>Switches</subject><subject>Voltage-controlled oscillators</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFZ_gHhZEI-pOzPZr2MJ2lQiFaLgbUniLqTYDzftof56U1K8zDDwvDPMw9gtiAmAsI8vZZlNUEA6QbQWNZ2xEUhpEtD0ec5GQoBJLApxya66btmPaWpgxB6mHA2f5b88P9Sx_eJvRcHbNSfk6xUvF3OevS7Ka3YRqu_O35z6mH08P71neVIsZvNsWiQNWtr1NSUbfKN8MLXyCmpvFKISUmlqVLDSBtloqcmQJfS6sgqNRhmkNpUnGrP7Ye82bn72vtu55WYf1_1JB7L_UxNp6CkYqCZuui764LaxXVXx4EC4ow13tOGONtzJRp-5GzKt9_6fVxoFQkp_nH5VDQ</recordid><startdate>20140401</startdate><enddate>20140401</enddate><creator>Ferriss, Mark</creator><creator>Rylyakov, Alexander</creator><creator>Tierno, Jose A.</creator><creator>Ainspan, Herschel</creator><creator>Friedman, Daniel J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is -110 dBc/Hz at 10 MHz offset. The 14 × 160 μm 2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2014.2299273</doi><tpages>9</tpages></addata></record>
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subjects	Capacitors Charge pumps Clocks DPLL frequency synthesizers hybrid PLL Noise phase locked loop Phase locked loops PLL Switches Voltage-controlled oscillators
title	A 28 GHz Hybrid PLL in 32 nm SOI CMOS
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