Design of a low-power digital processor for a security passive RFID tag
A digital processor in secure RFID tag is designed to support a cryptographic data communication between an interrogator and a tag. The AES OFB-like algorithm is used for a cryptographic data communication. The digital processor is fully compatible with the EPC C1 G2 protocol. The power consumption...
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| creator | Taehun Ki Hyunseok Kim Chelho Chung Young-Han Kim Kyusung Bae Jongbae Kim |
| description | A digital processor in secure RFID tag is designed to support a cryptographic data communication between an interrogator and a tag. The AES OFB-like algorithm is used for a cryptographic data communication. The digital processor is fully compatible with the EPC C1 G2 protocol. The power consumption of the digital processor is optimized to maintain the minimum sensitivity level for both the insecure and secure communication. In the simulation results, the power consumption is 2.43μW and 3.14μW in the insecure and the secure communication, respectively. |
| doi_str_mv | 10.1109/IECON.2013.6700023 |
| format | Conference Proceeding |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | A security RFID tag Advanced Encryption Standard (AES) Clocks Cryptography Engines Low power CMOS digital circuit Power demand Protocols Radiofrequency identification |
| title | Design of a low-power digital processor for a security passive RFID tag |
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