Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS
This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 505 |
|---|---|
| container_issue | |
| container_start_page | 503 |
| container_title | |
| container_volume | |
| creator | Anh Trong Huynh Hoa Thai Duong Hoang Viet Le Skafidas, Efstratios |
| description | This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits. |
| doi_str_mv | 10.1109/APMC.2013.6694845 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6694845</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6694845</ieee_id><sourcerecordid>6694845</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-5dbd71ec5598878c44407b14fb43d3f807468ce1fbdd65b4b078678d9f47cbf13</originalsourceid><addsrcrecordid>eNo9kMFKAzEYhKMoWOo-gHjJC2xNNn_yJ8clq1VorVg9lySbaKTblt1F8O0tWDzMzMcc5jCE3HA245yZu_plaWcV42KmlAEN8owUBjUHNOZoVXVOJhVXsgQEcfHPFV6RYhi-GGMcUUohJ-S5iUP-2NF9oo4Gd3Ahj_k70qa2tMtD58bweey32fdu3Pc0HTUctnmk6_qV1o2leUeVpLuO2uVqfU0uk9sOsTjllLw_3L_Zx3Kxmj_ZelFmjnIsZetb5DFIabRGHQCAoeeQPIhWJM0QlA6RJ9-2SnrwDLVC3ZoEGHziYkpu_3ZzjHFz6HPn-p_N6Q3xC8V9Tko</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Anh Trong Huynh ; Hoa Thai Duong ; Hoang Viet Le ; Skafidas, Efstratios</creator><creatorcontrib>Anh Trong Huynh ; Hoa Thai Duong ; Hoang Viet Le ; Skafidas, Efstratios</creatorcontrib><description>This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits.</description><identifier>ISSN: 2165-4727</identifier><identifier>EISSN: 2165-4743</identifier><identifier>EISBN: 9781479914722</identifier><identifier>EISBN: 147991472X</identifier><identifier>DOI: 10.1109/APMC.2013.6694845</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analog to digital converter ; Approximation methods ; Arrays ; Calibration ; Capacitance ; capacitor mismatch ; Capacitors ; complementary metal oxide semiconductor ; Distortion measurement ; Frequency measurement ; successive approximation register</subject><ispartof>2013 Asia-Pacific Microwave Conference Proceedings (APMC), 2013, p.503-505</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6694845$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6694845$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Anh Trong Huynh</creatorcontrib><creatorcontrib>Hoa Thai Duong</creatorcontrib><creatorcontrib>Hoang Viet Le</creatorcontrib><creatorcontrib>Skafidas, Efstratios</creatorcontrib><title>Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS</title><title>2013 Asia-Pacific Microwave Conference Proceedings (APMC)</title><addtitle>APMC</addtitle><description>This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits.</description><subject>Analog to digital converter</subject><subject>Approximation methods</subject><subject>Arrays</subject><subject>Calibration</subject><subject>Capacitance</subject><subject>capacitor mismatch</subject><subject>Capacitors</subject><subject>complementary metal oxide semiconductor</subject><subject>Distortion measurement</subject><subject>Frequency measurement</subject><subject>successive approximation register</subject><issn>2165-4727</issn><issn>2165-4743</issn><isbn>9781479914722</isbn><isbn>147991472X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kMFKAzEYhKMoWOo-gHjJC2xNNn_yJ8clq1VorVg9lySbaKTblt1F8O0tWDzMzMcc5jCE3HA245yZu_plaWcV42KmlAEN8owUBjUHNOZoVXVOJhVXsgQEcfHPFV6RYhi-GGMcUUohJ-S5iUP-2NF9oo4Gd3Ahj_k70qa2tMtD58bweey32fdu3Pc0HTUctnmk6_qV1o2leUeVpLuO2uVqfU0uk9sOsTjllLw_3L_Zx3Kxmj_ZelFmjnIsZetb5DFIabRGHQCAoeeQPIhWJM0QlA6RJ9-2SnrwDLVC3ZoEGHziYkpu_3ZzjHFz6HPn-p_N6Q3xC8V9Tko</recordid><startdate>201311</startdate><enddate>201311</enddate><creator>Anh Trong Huynh</creator><creator>Hoa Thai Duong</creator><creator>Hoang Viet Le</creator><creator>Skafidas, Efstratios</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201311</creationdate><title>Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS</title><author>Anh Trong Huynh ; Hoa Thai Duong ; Hoang Viet Le ; Skafidas, Efstratios</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-5dbd71ec5598878c44407b14fb43d3f807468ce1fbdd65b4b078678d9f47cbf13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Analog to digital converter</topic><topic>Approximation methods</topic><topic>Arrays</topic><topic>Calibration</topic><topic>Capacitance</topic><topic>capacitor mismatch</topic><topic>Capacitors</topic><topic>complementary metal oxide semiconductor</topic><topic>Distortion measurement</topic><topic>Frequency measurement</topic><topic>successive approximation register</topic><toplevel>online_resources</toplevel><creatorcontrib>Anh Trong Huynh</creatorcontrib><creatorcontrib>Hoa Thai Duong</creatorcontrib><creatorcontrib>Hoang Viet Le</creatorcontrib><creatorcontrib>Skafidas, Efstratios</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Anh Trong Huynh</au><au>Hoa Thai Duong</au><au>Hoang Viet Le</au><au>Skafidas, Efstratios</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS</atitle><btitle>2013 Asia-Pacific Microwave Conference Proceedings (APMC)</btitle><stitle>APMC</stitle><date>2013-11</date><risdate>2013</risdate><spage>503</spage><epage>505</epage><pages>503-505</pages><issn>2165-4727</issn><eissn>2165-4743</eissn><eisbn>9781479914722</eisbn><eisbn>147991472X</eisbn><abstract>This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits.</abstract><pub>IEEE</pub><doi>10.1109/APMC.2013.6694845</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2165-4727 |
| ispartof | 2013 Asia-Pacific Microwave Conference Proceedings (APMC), 2013, p.503-505 |
| issn | 2165-4727 2165-4743 |
| language | eng |
| recordid | cdi_ieee_primary_6694845 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog to digital converter Approximation methods Arrays Calibration Capacitance capacitor mismatch Capacitors complementary metal oxide semiconductor Distortion measurement Frequency measurement successive approximation register |
| title | Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T19%3A20%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design%20of%20a%20capacitive%20DAC%20mismatch%20calibrator%20for%20split%20SAR%20ADC%20in%2065%20nm%20CMOS&rft.btitle=2013%20Asia-Pacific%20Microwave%20Conference%20Proceedings%20(APMC)&rft.au=Anh%20Trong%20Huynh&rft.date=2013-11&rft.spage=503&rft.epage=505&rft.pages=503-505&rft.issn=2165-4727&rft.eissn=2165-4743&rft_id=info:doi/10.1109/APMC.2013.6694845&rft_dat=%3Cieee_6IE%3E6694845%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781479914722&rft.eisbn_list=147991472X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6694845&rfr_iscdi=true |