Enhanced FPGA based three level space vector pulse width modulation with active neutral point balancing

Enhanced FPGA based three level space vector pulse width modulation with active neutral point balancing

This paper presents an FPGA based implementation of an improved space vector pulse width modulation for neutral point clamped three-level topologies. For this purpose the flatspace modulation calculating the timings is used in combination with an optimized switching pattern to reduce the switching e...

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Hauptverfasser: Bartsch, Alexander, Senicar, Florian, Kratz, Sascha, Soter, Stefan
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Sprache:eng
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Field programmable gate arrays
Inverters
Space vector pulse width modulation
Switches
Topology
Vectors
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creator Bartsch, Alexander
Senicar, Florian
Kratz, Sascha
Soter, Stefan
description This paper presents an FPGA based implementation of an improved space vector pulse width modulation for neutral point clamped three-level topologies. For this purpose the flatspace modulation calculating the timings is used in combination with an optimized switching pattern to reduce the switching edges to a minimum. Additionally a combination of two methods for balancing the neutral point is developed which are both implemented without adding any additional harmonics to the modulated output.
doi_str_mv 10.1109/ECCE.2013.6646918
format Conference Proceeding
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subjects Field programmable gate arrays
Inverters
Space vector pulse width modulation
Switches
Topology
Vectors
title Enhanced FPGA based three level space vector pulse width modulation with active neutral point balancing
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