A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm

The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasin...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2014-01, Vol.49 (1), p.19-31
Hauptverfasser:	Hart, Jason M., Hoyeol Cho, Yuefei Ge, Gruber, Gregory, Dawei Huang, Changku Hwang, Jian, Daisy, Johnson, Tim, Konstadinidis, Georgios K., Krishnaswamy, Venkat, Kwong, Lance, Masleid, Robert P., Mehta, Rakesh, Nawathe, Umesh, Ramachandran, Aparna, Sathianathan, Hari, Yongning Sheng, Shin, Jinuk Luke, Turullols, Sebastian, Zuxu Qin, Yen, King C.
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog circuit Bandwidth Clocks digital circuit Layout Metals microprocessor multi-core multi-threaded SPARC system on chip (SoC) System-on-chip Timing Transistors very large scale integration (VLSI)
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