Neuron Array With Plastic Synapses and Programmable Dendrites
We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-...
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Veröffentlicht in: | IEEE transactions on biomedical circuits and systems 2013-10, Vol.7 (5), p.631-642 |
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creator | Ramakrishnan, Shubha Wunderlich, Richard Hasler, Jennifer George, Suma |
description | We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition. |
doi_str_mv | 10.1109/TBCAS.2013.2282616 |
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(IEEE) Oct 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c466t-fab54b3d9e29fa672714d285d1276ede3e5a49b2d271e0baa38288ddc78247ee3</citedby><cites>FETCH-LOGICAL-c466t-fab54b3d9e29fa672714d285d1276ede3e5a49b2d271e0baa38288ddc78247ee3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6637106$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6637106$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://www.ncbi.nlm.nih.gov/pubmed/24144669$$D View this record in MEDLINE/PubMed$$Hfree_for_read</backlink></links><search><creatorcontrib>Ramakrishnan, Shubha</creatorcontrib><creatorcontrib>Wunderlich, Richard</creatorcontrib><creatorcontrib>Hasler, Jennifer</creatorcontrib><creatorcontrib>George, Suma</creatorcontrib><title>Neuron Array With Plastic Synapses and Programmable Dendrites</title><title>IEEE transactions on biomedical circuits and systems</title><addtitle>TBCAS</addtitle><addtitle>IEEE Trans Biomed Circuits Syst</addtitle><description>We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.</description><subject>Arrays</subject><subject>Channels</subject><subject>Chips</subject><subject>Computational efficiency</subject><subject>Computational modeling</subject><subject>Dendrites - physiology</subject><subject>Dendritic computation and processing</subject><subject>Dendritic structure</subject><subject>field programmable analog arrays (FPAA)</subject><subject>Field programmable gate arrays</subject><subject>floating-gate devices</subject><subject>Mathematical models</subject><subject>Microarray Analysis - instrumentation</subject><subject>Models, Neurological</subject><subject>Neural Networks (Computer)</subject><subject>Neurons</subject><subject>Neurons - physiology</subject><subject>on-chip learning</subject><subject>Plastics</subject><subject>Routing</subject><subject>Synapses</subject><subject>Synapses - physiology</subject><issn>1932-4545</issn><issn>1940-9990</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><sourceid>EIF</sourceid><recordid>eNqNkctLHEEQh5sQ8bH6DyQQBrx4mbW7-n3IYV2fICqo5Dj0TNcmI_NYu2cO-9_b6248eElOVVDfr4riI-Qbo1PGqD19OpvPHqdAGZ8CGFBMfSH7zAqaW2vp13XPIRdSyD1yEOMLpVKBhV2yB4IJoZTdJz_vcAx9l81CcKvsVz38yR4aF4e6yh5XnVtGjJnrfPYQ-t_Bta0rG8zOsfOhHjAekp2FayIebeuEPF9ePM2v89v7q5v57Dav0pUhX7hSipJ7i2AXTmnQTHgw0jPQCj1ylE7YEnwaIC2d4waM8b7SBoRG5BNystm7DP3riHEo2jpW2DSuw36MBVNGai2Mhv9AteKKS0H_jQppmbRKmoQef0Jf-jF06edECS00A6USBRuqCn2MARfFMtStC6uC0WKtrHhXVqyVFVtlKfRju3osW_Qfkb-OEvB9A9SI-DFO5zSjir8BQCyYAA</recordid><startdate>20131001</startdate><enddate>20131001</enddate><creator>Ramakrishnan, Shubha</creator><creator>Wunderlich, Richard</creator><creator>Hasler, Jennifer</creator><creator>George, Suma</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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subjects | Arrays Channels Chips Computational efficiency Computational modeling Dendrites - physiology Dendritic computation and processing Dendritic structure field programmable analog arrays (FPAA) Field programmable gate arrays floating-gate devices Mathematical models Microarray Analysis - instrumentation Models, Neurological Neural Networks (Computer) Neurons Neurons - physiology on-chip learning Plastics Routing Synapses Synapses - physiology |
title | Neuron Array With Plastic Synapses and Programmable Dendrites |
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