Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications

Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al x Ga 1-x Sb TFETs is investigated, showing that cross-sections up to 10nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an "optimal" design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (I O n) of 175μA/μm.