Power reduction by aggressive synthesis design space exploration
An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of pa...
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| creator | Ziegler, Matthew M. Gristede, George D. Zyuban, Victor V. |
| description | An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of parallel synthesis job submission for design space exploration. By tailoring the design flow for parallel and iterative design space exploration we attempt to maximize the return on investment (ROI) of design effort. The methodology was applied to the IBM POWER7+™ microprocessor to save power during the second release of the chip. This paper provides an overview of the methodology as well as chip hardware measurements showing power savings. |
| doi_str_mv | 10.1109/ISLPED.2013.6629335 |
| format | Conference Proceeding |
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This paper provides an overview of the methodology as well as chip hardware measurements showing power savings.</description><subject>Design methodology</subject><subject>Low Power Design</subject><subject>Optimization</subject><subject>Space exploration</subject><subject>Synthesis</subject><subject>Timing</subject><subject>Tuners</subject><isbn>1479912344</isbn><isbn>9781479912353</isbn><isbn>1479912352</isbn><isbn>9781479912346</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tOwzAQRc0CqVD6Bd34BxI8GSeOd6BSaKVIVKL7yonHqVFJIjs88vcU0c25q3Olw9gSRAog9P32rdqtn9JMAKZFkWnE_IrdglRaQ4ZSztgixnchBCiVy1zesIdd_02BB7Kfzej7jtcTN20bKEb_RTxO3Xik6CO3Z7Ydj4NpiNPPcOqD-RPu2LUzp0iLy87Z_nm9X22S6vVlu3qsEq_FmJQWETJVSCSVYV4UUpfa2dIoWZeuMYKstg2BUTU0kKNWCE4TauGcVeeQOVv-33oiOgzBf5gwHS6N-AupZEiq</recordid><startdate>201309</startdate><enddate>201309</enddate><creator>Ziegler, Matthew M.</creator><creator>Gristede, George D.</creator><creator>Zyuban, Victor V.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201309</creationdate><title>Power reduction by aggressive synthesis design space exploration</title><author>Ziegler, Matthew M. ; Gristede, George D. ; Zyuban, Victor V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8d33127643e7235664989fd8a74b8fca0ed9dce1a7b1c1539731f9e390ffd7293</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Design methodology</topic><topic>Low Power Design</topic><topic>Optimization</topic><topic>Space exploration</topic><topic>Synthesis</topic><topic>Timing</topic><topic>Tuners</topic><toplevel>online_resources</toplevel><creatorcontrib>Ziegler, Matthew M.</creatorcontrib><creatorcontrib>Gristede, George D.</creatorcontrib><creatorcontrib>Zyuban, Victor V.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ziegler, Matthew M.</au><au>Gristede, George D.</au><au>Zyuban, Victor V.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power reduction by aggressive synthesis design space exploration</atitle><btitle>International Symposium on Low Power Electronics and Design (ISLPED)</btitle><stitle>ISLPED</stitle><date>2013-09</date><risdate>2013</risdate><spage>421</spage><epage>426</epage><pages>421-426</pages><eisbn>1479912344</eisbn><eisbn>9781479912353</eisbn><eisbn>1479912352</eisbn><eisbn>9781479912346</eisbn><abstract>An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of parallel synthesis job submission for design space exploration. By tailoring the design flow for parallel and iterative design space exploration we attempt to maximize the return on investment (ROI) of design effort. The methodology was applied to the IBM POWER7+™ microprocessor to save power during the second release of the chip. This paper provides an overview of the methodology as well as chip hardware measurements showing power savings.</abstract><pub>IEEE</pub><doi>10.1109/ISLPED.2013.6629335</doi><tpages>6</tpages></addata></record> |
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| ispartof | International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.421-426 |
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| language | eng |
| recordid | cdi_ieee_primary_6629335 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Design methodology Low Power Design Optimization Space exploration Synthesis Timing Tuners |
| title | Power reduction by aggressive synthesis design space exploration |
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