Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth
To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The chan...
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| Veröffentlicht in: | IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2014-02, Vol.4 (2), p.268-278 |
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| container_title | IEEE transactions on components, packaging, and manufacturing technology (2011) |
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| creator | Ki Jin Han Xiaoxiong Gu Kwark, Young H. Lei Shan Ritter, Mark B. |
| description | To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth. |
| doi_str_mv | 10.1109/TCPMT.2013.2277291 |
| format | Article |
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A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.</description><identifier>ISSN: 2156-3950</identifier><identifier>EISSN: 2156-3985</identifier><identifier>DOI: 10.1109/TCPMT.2013.2277291</identifier><identifier>CODEN: ITCPC8</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Aggregate data bandwidth ; backdrilling ; Bandwidth ; baud rate ; Channel estimation ; Channel models ; channel reach ; Data models ; design guideline ; equalization ; Guidelines ; high-speed links ; Integrated circuit modeling ; Manufacturing ; multilayered board ; multiple package modules ; parametric simulation ; particle swarm optimization (PSO) ; Product introduction ; Serializer/Deserializer (SerDes) ; transmission line loss ; via stub effect</subject><ispartof>IEEE transactions on components, packaging, and manufacturing technology (2011), 2014-02, Vol.4 (2), p.268-278</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Feb 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-39d21ae13dbea9e756c0b3337928d0252d835e41a1028a7a8e9ad17200157da3</citedby><cites>FETCH-LOGICAL-c295t-39d21ae13dbea9e756c0b3337928d0252d835e41a1028a7a8e9ad17200157da3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6584771$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6584771$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ki Jin Han</creatorcontrib><creatorcontrib>Xiaoxiong Gu</creatorcontrib><creatorcontrib>Kwark, Young H.</creatorcontrib><creatorcontrib>Lei Shan</creatorcontrib><creatorcontrib>Ritter, Mark B.</creatorcontrib><title>Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth</title><title>IEEE transactions on components, packaging, and manufacturing technology (2011)</title><addtitle>TCPMT</addtitle><description>To achieve a target data bandwidth in high-speed channels, an on-board channel modeling study was presented in this paper. A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.</description><subject>Aggregate data bandwidth</subject><subject>backdrilling</subject><subject>Bandwidth</subject><subject>baud rate</subject><subject>Channel estimation</subject><subject>Channel models</subject><subject>channel reach</subject><subject>Data models</subject><subject>design guideline</subject><subject>equalization</subject><subject>Guidelines</subject><subject>high-speed links</subject><subject>Integrated circuit modeling</subject><subject>Manufacturing</subject><subject>multilayered board</subject><subject>multiple package modules</subject><subject>parametric simulation</subject><subject>particle swarm optimization (PSO)</subject><subject>Product introduction</subject><subject>Serializer/Deserializer (SerDes)</subject><subject>transmission line loss</subject><subject>via stub effect</subject><issn>2156-3950</issn><issn>2156-3985</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1PwkAQhhujiUT5A3rZxHNxZ5fttkfAD0wgmNB43QzdgS7BFneLxn9vK4S5zBzeZ2byRNEd8AEAzx7zyfs8HwgOciCE1iKDi6gnQCWxzFJ1eZ4Vv476IWx5WyrlmstehPPa0s5VG7ao4nGN3rIPh2zZHFaBYWVZ7rGgwFzFpm5Txss9kWWTEquKdoGta89GRenou1vRJcizJ2yQjVv4x9mmvI2u1rgL1D_1myh_ec4n03i2eH2bjGZxITLVtO9ZAUgg7YowI62Sgq-klDoTqeVCCZtKRUNA4CJFjSllaEELzkFpi_Imejiu3fv660ChMdv64Kv2ogHFFQg-TGSbEsdU4esQPK3N3rtP9L8GuOlkmn-ZppNpTjJb6P4IOSI6A4lKh1qD_APEzW5J</recordid><startdate>20140201</startdate><enddate>20140201</enddate><creator>Ki Jin Han</creator><creator>Xiaoxiong Gu</creator><creator>Kwark, Young H.</creator><creator>Lei Shan</creator><creator>Ritter, Mark B.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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A design guideline was found by observing the variation of link performance, depending on parameters such as channel length, baud rate, and the number of signal layers. The channel performance was investigated using a newly developed parametric simulation environment supported by a fast multilayered via transition modeling tool. The extensive parameter sweep simulations showed that an allowable channel reach has a lower and an upper bound limited by stub via effect and trace loss, respectively. Under a specified channel reach, the aggregate data bandwidths were estimated using a particle swarm optimization routine, and a tradeoff relation among the wiring capability and the maximum allowable data rate was observed. From these observations, the approach provides a guideline to select the number of signal layers for achieving the required data bandwidth.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/TCPMT.2013.2277291</doi><tpages>11</tpages></addata></record> |
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| subjects | Aggregate data bandwidth backdrilling Bandwidth baud rate Channel estimation Channel models channel reach Data models design guideline equalization Guidelines high-speed links Integrated circuit modeling Manufacturing multilayered board multiple package modules parametric simulation particle swarm optimization (PSO) Product introduction Serializer/Deserializer (SerDes) transmission line loss via stub effect |
| title | Modeling On-Board Via Stubs and Traces in High-Speed Channels for Achieving Higher Data Bandwidth |
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