Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not onl...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2014-06, Vol.22 (6), p.1455-1459
Hauptverfasser:	Garcia-Herrero, Francisco, Canet, Maria Jose, Valls, Javier
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer architecture Decoding Error correction codes hardware architecture iterative decoding Microprocessors nonbinary low-density parity-check codes Parity check codes Reliability symbol flipping decoding Throughput Very large scale integration
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