A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS

This paper presents a turbo-decoder ASIC for 3GPP LTE-Advanced supporting all specified code rates and block sizes. The highly parallelized architecture employs 16 SISO decoders with an optimized state-metric initialization scheme that reduces SISO-decoder latency, which is key for achieving very-high throughput. A novel CRC implementation for parallel turbo decoding prevents the decoder from performing redundant turbo iterations. The 65nm ASIC achieves a record data throughput of 1.013Gbps at 5.5 iterations with unprecedented energy efficiency of 0.17nJ/bit/iter.