64nm pitch interconnects: Optimized for designability, manufacturability and extendibility

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been "plugged in" to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.