0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of...
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| creator | Nomura, M. Muramatsu, A. Takeno, H. Hattori, S. Ogawa, D. Nasu, M. Hirairi, K. Kumashiro, S. Moriwaki, S. Yamamoto, Y. Miyano, S. Hiraku, Y. Hayashi, I. Yoshioka, K. Shikata, A. Ishikuro, H. Ahn, M. Okuma, Y. Zhang, X. Ryu, Y. Ishida, K. Takamiya, M. Kuroda, T. Shinohara, H. Sakurai, T. |
| description | A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. |
| format | Conference Proceeding |
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In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.</description><subject>Central Processing Unit</subject><subject>Clocks</subject><subject>Delays</subject><subject>Energy efficiency</subject><subject>Frequency measurement</subject><subject>Logic circuits</subject><issn>0743-1562</issn><isbn>9781467352260</isbn><isbn>1467352268</isbn><isbn>9784863483477</isbn><isbn>4863483473</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMtOwkAYhWvURESewM2_hEV1OvdZkiKXBAJJEZdkOp3CaGmxUzC8iY-riKuTs_i-k5yroKOEpJITKgkV4vqvR5QLwjDm6CZoIUFJGDGO74J7798RwogR2Qq-0RNbgdvpjYV9XRnrfVXDl2u2wDiB0XyRPL9BMpkNQJcZEJy6BuLFKxy8KzewdZstHKuiOfOmqMwHZM43tUsPjatK6I5X8aD3h-pM7xt3tJDX9vNgS3MCb3RxtnT7w6R3GaWo3EE8mycPwW2uC287_9kOlsOXZTwOp_PRJO5PQ6dQE6pMasxVxJWRKSJRalJlDGWRoAwrybDF3OKIIaMUlYgLo7Qy2BiD8txQRNrB40XrrLXrff37RH1acyY4jxT5AYUfYRs</recordid><startdate>201306</startdate><enddate>201306</enddate><creator>Nomura, M.</creator><creator>Muramatsu, A.</creator><creator>Takeno, H.</creator><creator>Hattori, S.</creator><creator>Ogawa, D.</creator><creator>Nasu, M.</creator><creator>Hirairi, K.</creator><creator>Kumashiro, S.</creator><creator>Moriwaki, S.</creator><creator>Yamamoto, Y.</creator><creator>Miyano, S.</creator><creator>Hiraku, Y.</creator><creator>Hayashi, I.</creator><creator>Yoshioka, K.</creator><creator>Shikata, A.</creator><creator>Ishikuro, H.</creator><creator>Ahn, M.</creator><creator>Okuma, Y.</creator><creator>Zhang, X.</creator><creator>Ryu, Y.</creator><creator>Ishida, K.</creator><creator>Takamiya, M.</creator><creator>Kuroda, T.</creator><creator>Shinohara, H.</creator><creator>Sakurai, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201306</creationdate><title>0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS</title><author>Nomura, M. ; Muramatsu, A. ; Takeno, H. ; Hattori, S. ; Ogawa, D. ; Nasu, M. ; Hirairi, K. ; Kumashiro, S. ; Moriwaki, S. ; Yamamoto, Y. ; Miyano, S. ; Hiraku, Y. ; Hayashi, I. ; Yoshioka, K. ; Shikata, A. ; Ishikuro, H. ; Ahn, M. ; Okuma, Y. ; Zhang, X. ; Ryu, Y. ; Ishida, K. ; Takamiya, M. ; Kuroda, T. ; Shinohara, H. ; Sakurai, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-9d8a269169c8b031bcb9cc45174529852e26e2150c9948067c9a9c2ccc0ffc403</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Central Processing Unit</topic><topic>Clocks</topic><topic>Delays</topic><topic>Energy efficiency</topic><topic>Frequency measurement</topic><topic>Logic circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Nomura, M.</creatorcontrib><creatorcontrib>Muramatsu, A.</creatorcontrib><creatorcontrib>Takeno, H.</creatorcontrib><creatorcontrib>Hattori, S.</creatorcontrib><creatorcontrib>Ogawa, D.</creatorcontrib><creatorcontrib>Nasu, M.</creatorcontrib><creatorcontrib>Hirairi, K.</creatorcontrib><creatorcontrib>Kumashiro, S.</creatorcontrib><creatorcontrib>Moriwaki, S.</creatorcontrib><creatorcontrib>Yamamoto, Y.</creatorcontrib><creatorcontrib>Miyano, S.</creatorcontrib><creatorcontrib>Hiraku, Y.</creatorcontrib><creatorcontrib>Hayashi, I.</creatorcontrib><creatorcontrib>Yoshioka, K.</creatorcontrib><creatorcontrib>Shikata, A.</creatorcontrib><creatorcontrib>Ishikuro, H.</creatorcontrib><creatorcontrib>Ahn, M.</creatorcontrib><creatorcontrib>Okuma, Y.</creatorcontrib><creatorcontrib>Zhang, X.</creatorcontrib><creatorcontrib>Ryu, Y.</creatorcontrib><creatorcontrib>Ishida, K.</creatorcontrib><creatorcontrib>Takamiya, M.</creatorcontrib><creatorcontrib>Kuroda, T.</creatorcontrib><creatorcontrib>Shinohara, H.</creatorcontrib><creatorcontrib>Sakurai, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nomura, M.</au><au>Muramatsu, A.</au><au>Takeno, H.</au><au>Hattori, S.</au><au>Ogawa, D.</au><au>Nasu, M.</au><au>Hirairi, K.</au><au>Kumashiro, S.</au><au>Moriwaki, S.</au><au>Yamamoto, Y.</au><au>Miyano, S.</au><au>Hiraku, Y.</au><au>Hayashi, I.</au><au>Yoshioka, K.</au><au>Shikata, A.</au><au>Ishikuro, H.</au><au>Ahn, M.</au><au>Okuma, Y.</au><au>Zhang, X.</au><au>Ryu, Y.</au><au>Ishida, K.</au><au>Takamiya, M.</au><au>Kuroda, T.</au><au>Shinohara, H.</au><au>Sakurai, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS</atitle><btitle>2013 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2013-06</date><risdate>2013</risdate><spage>C36</spage><epage>C37</epage><pages>C36-C37</pages><issn>0743-1562</issn><isbn>9781467352260</isbn><isbn>1467352268</isbn><eisbn>9784863483477</eisbn><eisbn>4863483473</eisbn><abstract>A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.</abstract><pub>IEEE</pub></addata></record> |
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| subjects | Central Processing Unit Clocks Delays Energy efficiency Frequency measurement Logic circuits |
| title | 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS |
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