Impact of wafer thinning on High-K Metal Gate 20nm devices

In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100μm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshol...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Beece, Adam, Agarwal, Rahul, Chandrashekhar, Sandhya, Singh, Jagar, Siddhartha, Siddhartha, Alapati, Ramakanth, Parameshwaran, Biju, Dumas, Jeff, Alvanos, Tyson
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Coatings Logic gates MOS devices Packaging Semiconductor device reliability Silicon
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