Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment

This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Goncharov, M.V., Smirnov, A.B., Klotchkov, I.V., Starodoubtsev, N.A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Asynchronous circuits Circuit simulation Clocks Concurrent computing Delay Design methodology Logic design Logic testing Signal design Timing
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