Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment
This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavi...
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| creator | Goncharov, M.V. Smirnov, A.B. Klotchkov, I.V. Starodoubtsev, N.A. |
| description | This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavior specified by consistent and bounded timed STG in a VHDL environment is proposed. For illustration the paper presents the possible use of the VHDL-based STG representation in asynchronous circuit design. |
| doi_str_mv | 10.1109/CSD.1998.657545 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_657545</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>657545</ieee_id><sourcerecordid>657545</sourcerecordid><originalsourceid>FETCH-LOGICAL-i174t-bb908c81106dd71a98aedfce22929b7cf39ad4b5fd112fc4bfcc628c9f10a8fb3</originalsourceid><addsrcrecordid>eNotkM1KAzEYRQMiqLVrwdX3Ah2TyfwkS2m1FQouWl1a8vPFRiaJTGLRt7dY7-ZuDpfDJeSG0YoxKu_mm0XFpBRV1_Zt056RKyqY6ARvKb8g05w_6DFc8o6zS_K29cHHd8DvgjH7FDMkB5vtEkKyOICKFhQELPtkoSTIPnwNqiAUH9D-gRr36uDTCD7C62qxBowHP6YYMJZrcu7UkHH63xPy8viwna9m6-fl0_x-PfOsb8pMa0mFEUf_ztqeKSkUWmewrmUtdW8cl8o2unWWsdqZRjtjuloY6RhVwmk-IbenXY-Iu8_RBzX-7E4P8F8eB1Iw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Goncharov, M.V. ; Smirnov, A.B. ; Klotchkov, I.V. ; Starodoubtsev, N.A.</creator><creatorcontrib>Goncharov, M.V. ; Smirnov, A.B. ; Klotchkov, I.V. ; Starodoubtsev, N.A.</creatorcontrib><description>This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavior specified by consistent and bounded timed STG in a VHDL environment is proposed. For illustration the paper presents the possible use of the VHDL-based STG representation in asynchronous circuit design.</description><identifier>ISBN: 0818683503</identifier><identifier>ISBN: 9780818683503</identifier><identifier>DOI: 10.1109/CSD.1998.657545</identifier><language>eng</language><publisher>IEEE</publisher><subject>Asynchronous circuits ; Circuit simulation ; Clocks ; Concurrent computing ; Delay ; Design methodology ; Logic design ; Logic testing ; Signal design ; Timing</subject><ispartof>Proceedings 1998 International Conference on Application of Concurrency to System Design, 1998, p.120-129</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/657545$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/657545$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Goncharov, M.V.</creatorcontrib><creatorcontrib>Smirnov, A.B.</creatorcontrib><creatorcontrib>Klotchkov, I.V.</creatorcontrib><creatorcontrib>Starodoubtsev, N.A.</creatorcontrib><title>Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment</title><title>Proceedings 1998 International Conference on Application of Concurrency to System Design</title><addtitle>CSD</addtitle><description>This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavior specified by consistent and bounded timed STG in a VHDL environment is proposed. For illustration the paper presents the possible use of the VHDL-based STG representation in asynchronous circuit design.</description><subject>Asynchronous circuits</subject><subject>Circuit simulation</subject><subject>Clocks</subject><subject>Concurrent computing</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Logic design</subject><subject>Logic testing</subject><subject>Signal design</subject><subject>Timing</subject><isbn>0818683503</isbn><isbn>9780818683503</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1KAzEYRQMiqLVrwdX3Ah2TyfwkS2m1FQouWl1a8vPFRiaJTGLRt7dY7-ZuDpfDJeSG0YoxKu_mm0XFpBRV1_Zt056RKyqY6ARvKb8g05w_6DFc8o6zS_K29cHHd8DvgjH7FDMkB5vtEkKyOICKFhQELPtkoSTIPnwNqiAUH9D-gRr36uDTCD7C62qxBowHP6YYMJZrcu7UkHH63xPy8viwna9m6-fl0_x-PfOsb8pMa0mFEUf_ztqeKSkUWmewrmUtdW8cl8o2unWWsdqZRjtjuloY6RhVwmk-IbenXY-Iu8_RBzX-7E4P8F8eB1Iw</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Goncharov, M.V.</creator><creator>Smirnov, A.B.</creator><creator>Klotchkov, I.V.</creator><creator>Starodoubtsev, N.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1998</creationdate><title>Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment</title><author>Goncharov, M.V. ; Smirnov, A.B. ; Klotchkov, I.V. ; Starodoubtsev, N.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i174t-bb908c81106dd71a98aedfce22929b7cf39ad4b5fd112fc4bfcc628c9f10a8fb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Asynchronous circuits</topic><topic>Circuit simulation</topic><topic>Clocks</topic><topic>Concurrent computing</topic><topic>Delay</topic><topic>Design methodology</topic><topic>Logic design</topic><topic>Logic testing</topic><topic>Signal design</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Goncharov, M.V.</creatorcontrib><creatorcontrib>Smirnov, A.B.</creatorcontrib><creatorcontrib>Klotchkov, I.V.</creatorcontrib><creatorcontrib>Starodoubtsev, N.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Goncharov, M.V.</au><au>Smirnov, A.B.</au><au>Klotchkov, I.V.</au><au>Starodoubtsev, N.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment</atitle><btitle>Proceedings 1998 International Conference on Application of Concurrency to System Design</btitle><stitle>CSD</stitle><date>1998</date><risdate>1998</risdate><spage>120</spage><epage>129</epage><pages>120-129</pages><isbn>0818683503</isbn><isbn>9780818683503</isbn><abstract>This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavior specified by consistent and bounded timed STG in a VHDL environment is proposed. For illustration the paper presents the possible use of the VHDL-based STG representation in asynchronous circuit design.</abstract><pub>IEEE</pub><doi>10.1109/CSD.1998.657545</doi><tpages>10</tpages></addata></record> |
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| ispartof | Proceedings 1998 International Conference on Application of Concurrency to System Design, 1998, p.120-129 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Asynchronous circuits Circuit simulation Clocks Concurrent computing Delay Design methodology Logic design Logic testing Signal design Timing |
| title | Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T07%3A41%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Timing%20extensions%20of%20STG%20model%20and%20a%20method%20to%20simulate%20timed%20STG%20behavior%20in%20VHDL%20environment&rft.btitle=Proceedings%201998%20International%20Conference%20on%20Application%20of%20Concurrency%20to%20System%20Design&rft.au=Goncharov,%20M.V.&rft.date=1998&rft.spage=120&rft.epage=129&rft.pages=120-129&rft.isbn=0818683503&rft.isbn_list=9780818683503&rft_id=info:doi/10.1109/CSD.1998.657545&rft_dat=%3Cieee_6IE%3E657545%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=657545&rfr_iscdi=true |