A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V Read-Port, and Offset Cell VDD Biasing Techniques

In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A * VDDmin for low-voltage applications. This L7T feature...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2013-10, Vol.48 (10), p.2558-2569
Hauptverfasser:	Meng-Fan Chang, Ming-Pin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Ching Wu, Tzu-Yi Yang, Yamauchi, Hiroyuki
Format:	Artikel
Sprache:	eng
Schlagworte:	Bit-line swing Clamps Hot carrier injection Layout low voltage read-port Sensors SRAM SRAM cells Transistors
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