An ultra-low-power voltage-mode asynchronous WTA-LTA circuit

An ultra-low-power voltage-mode asynchronous WTA-LTA circuit

This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Fernandez-Berni, Jorge, Carmona-Galan, Ricardo, Rodriquez-Vazquez, Angel
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Discharges (electric)
Neural networks
Parallel processing
Power demand
Switches
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 1820
container_issue
container_start_page 1817
container_title
container_volume
creator Fernandez-Berni, Jorge
Carmona-Galan, Ricardo
Rodriquez-Vazquez, Angel
description This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.
doi_str_mv 10.1109/ISCAS.2013.6572218
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6572218</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6572218</ieee_id><sourcerecordid>6572218</sourcerecordid><originalsourceid>FETCH-LOGICAL-i219t-38fc4d6843aed64309a09a2286135e1880715fccc7f8a27742c0864a793b03303</originalsourceid><addsrcrecordid>eNpVkMlKxEAURcsJDG1-QDf5gYrvvUoNATchODQEXHTEZVNWKhpJJ00Gm_57A_ZGuHAWFw6Xy9gtQowI6f16k2ebmABFrKQmQnPGwlQbTJQWUitU5ywglIajJHnxr4P0kgVAGnkigK5ZOI7fALB4FZIO2EPWRXM7DZa3_YHv-4Mfop--neyn57u-8pEdj537Gvqun8fovcx4UWaRawY3N9MNu6ptO_rwxBV7e3os8xdevD6v86zgDWE6cWFql1TKJML6Si07UruEyCgU0qMxoFHWzjldG0taJ-TAqMTqVHyAECBW7O7P23jvt_uh2dnhuD19IX4BJRpL7w</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An ultra-low-power voltage-mode asynchronous WTA-LTA circuit</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Fernandez-Berni, Jorge ; Carmona-Galan, Ricardo ; Rodriquez-Vazquez, Angel</creator><creatorcontrib>Fernandez-Berni, Jorge ; Carmona-Galan, Ricardo ; Rodriquez-Vazquez, Angel</creatorcontrib><description>This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 9781467357609</identifier><identifier>ISBN: 146735760X</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781467357616</identifier><identifier>EISBN: 1467357618</identifier><identifier>EISBN: 9781467357623</identifier><identifier>EISBN: 1467357626</identifier><identifier>DOI: 10.1109/ISCAS.2013.6572218</identifier><language>eng</language><publisher>IEEE</publisher><subject>Discharges (electric) ; Neural networks ; Parallel processing ; Power demand ; Switches ; Transistors</subject><ispartof>2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1817-1820</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6572218$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6572218$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Fernandez-Berni, Jorge</creatorcontrib><creatorcontrib>Carmona-Galan, Ricardo</creatorcontrib><creatorcontrib>Rodriquez-Vazquez, Angel</creatorcontrib><title>An ultra-low-power voltage-mode asynchronous WTA-LTA circuit</title><title>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.</description><subject>Discharges (electric)</subject><subject>Neural networks</subject><subject>Parallel processing</subject><subject>Power demand</subject><subject>Switches</subject><subject>Transistors</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9781467357609</isbn><isbn>146735760X</isbn><isbn>9781467357616</isbn><isbn>1467357618</isbn><isbn>9781467357623</isbn><isbn>1467357626</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMlKxEAURcsJDG1-QDf5gYrvvUoNATchODQEXHTEZVNWKhpJJ00Gm_57A_ZGuHAWFw6Xy9gtQowI6f16k2ebmABFrKQmQnPGwlQbTJQWUitU5ywglIajJHnxr4P0kgVAGnkigK5ZOI7fALB4FZIO2EPWRXM7DZa3_YHv-4Mfop--neyn57u-8pEdj537Gvqun8fovcx4UWaRawY3N9MNu6ptO_rwxBV7e3os8xdevD6v86zgDWE6cWFql1TKJML6Si07UruEyCgU0qMxoFHWzjldG0taJ-TAqMTqVHyAECBW7O7P23jvt_uh2dnhuD19IX4BJRpL7w</recordid><startdate>20130101</startdate><enddate>20130101</enddate><creator>Fernandez-Berni, Jorge</creator><creator>Carmona-Galan, Ricardo</creator><creator>Rodriquez-Vazquez, Angel</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20130101</creationdate><title>An ultra-low-power voltage-mode asynchronous WTA-LTA circuit</title><author>Fernandez-Berni, Jorge ; Carmona-Galan, Ricardo ; Rodriquez-Vazquez, Angel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i219t-38fc4d6843aed64309a09a2286135e1880715fccc7f8a27742c0864a793b03303</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Discharges (electric)</topic><topic>Neural networks</topic><topic>Parallel processing</topic><topic>Power demand</topic><topic>Switches</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Fernandez-Berni, Jorge</creatorcontrib><creatorcontrib>Carmona-Galan, Ricardo</creatorcontrib><creatorcontrib>Rodriquez-Vazquez, Angel</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fernandez-Berni, Jorge</au><au>Carmona-Galan, Ricardo</au><au>Rodriquez-Vazquez, Angel</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An ultra-low-power voltage-mode asynchronous WTA-LTA circuit</atitle><btitle>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2013-01-01</date><risdate>2013</risdate><spage>1817</spage><epage>1820</epage><pages>1817-1820</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9781467357609</isbn><isbn>146735760X</isbn><eisbn>9781467357616</eisbn><eisbn>1467357618</eisbn><eisbn>9781467357623</eisbn><eisbn>1467357626</eisbn><abstract>This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2013.6572218</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0271-4302
ispartof 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1817-1820
issn 0271-4302
2158-1525
language eng
recordid cdi_ieee_primary_6572218
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Discharges (electric)
Neural networks
Parallel processing
Power demand
Switches
Transistors
title An ultra-low-power voltage-mode asynchronous WTA-LTA circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T04%3A14%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20ultra-low-power%20voltage-mode%20asynchronous%20WTA-LTA%20circuit&rft.btitle=2013%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Fernandez-Berni,%20Jorge&rft.date=2013-01-01&rft.spage=1817&rft.epage=1820&rft.pages=1817-1820&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=9781467357609&rft.isbn_list=146735760X&rft_id=info:doi/10.1109/ISCAS.2013.6572218&rft_dat=%3Cieee_6IE%3E6572218%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467357616&rft.eisbn_list=1467357618&rft.eisbn_list=9781467357623&rft.eisbn_list=1467357626&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6572218&rfr_iscdi=true