Phase-locked loop based PWM wireless transmitter
A Cartesian transmitter based on pulse width modulation, with the capability to drive a switched power amplifier, such as a Class D stage, is presented. A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is s...
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| creator | Jingxue Lu Gharpurey, Ranjit |
| description | A Cartesian transmitter based on pulse width modulation, with the capability to drive a switched power amplifier, such as a Class D stage, is presented. A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is subsequently upconverted and applied to the output stage. This technique does not require a ramp generator or a high-precision voltage comparator, that are typically employed in conventional pulse width modulators. A prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a center frequency of 900 MHz. Operation of the architecture with modulation that has a non-constant envelope is verified in simulation. |
| doi_str_mv | 10.1109/ISCAS.2013.6571811 |
| format | Conference Proceeding |
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A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is subsequently upconverted and applied to the output stage. This technique does not require a ramp generator or a high-precision voltage comparator, that are typically employed in conventional pulse width modulators. A prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a center frequency of 900 MHz. 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A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is subsequently upconverted and applied to the output stage. This technique does not require a ramp generator or a high-precision voltage comparator, that are typically employed in conventional pulse width modulators. A prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a center frequency of 900 MHz. Operation of the architecture with modulation that has a non-constant envelope is verified in simulation.</description><subject>Bandwidth</subject><subject>Cartesian Transmitters</subject><subject>Frequency modulation</subject><subject>Mixers</subject><subject>PLL</subject><subject>Pulse width modulation</subject><subject>PWM</subject><subject>Switches</subject><subject>Transmitters</subject><subject>WCDMA</subject><subject>Wireless</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9781467357609</isbn><isbn>146735760X</isbn><isbn>9781467357616</isbn><isbn>1467357618</isbn><isbn>9781467357623</isbn><isbn>1467357626</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVj1tLw0AUhNcbGGr-gL7kD2w8Zzd7eyzBS6FioYqPZTd7gtHUlGxA_PcG7ItPA98Mwwxj1wglIrjb1bZebksBKEutDFrEE5Y7Y7HSRiqjUZ-yTKCyHJVQZ_88cOcsA2GQVxLEJctT-gCAuVejMBmDzbtPxPuh-aRY9MNwKMIMYrF5eyq-u5F6SqmYRv-V9t000XjFLlrfJ8qPumCv93cv9SNfPz-s6uWad2jUxOchNtomNOjQON86VFFbW6EKJC0KJJTBtEKYINvYyCCCFzN3EVRbzZkFu_nr7Yhodxi7vR9_dsf_8hc5j0in</recordid><startdate>201305</startdate><enddate>201305</enddate><creator>Jingxue Lu</creator><creator>Gharpurey, Ranjit</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201305</creationdate><title>Phase-locked loop based PWM wireless transmitter</title><author>Jingxue Lu ; Gharpurey, Ranjit</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-5258d8cbc19179af915d688415be38121e13b7f227b3fdc3b2ba28129d05f4be3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Bandwidth</topic><topic>Cartesian Transmitters</topic><topic>Frequency modulation</topic><topic>Mixers</topic><topic>PLL</topic><topic>Pulse width modulation</topic><topic>PWM</topic><topic>Switches</topic><topic>Transmitters</topic><topic>WCDMA</topic><topic>Wireless</topic><toplevel>online_resources</toplevel><creatorcontrib>Jingxue Lu</creatorcontrib><creatorcontrib>Gharpurey, Ranjit</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jingxue Lu</au><au>Gharpurey, Ranjit</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Phase-locked loop based PWM wireless transmitter</atitle><btitle>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2013-05</date><risdate>2013</risdate><spage>177</spage><epage>180</epage><pages>177-180</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9781467357609</isbn><isbn>146735760X</isbn><eisbn>9781467357616</eisbn><eisbn>1467357618</eisbn><eisbn>9781467357623</eisbn><eisbn>1467357626</eisbn><abstract>A Cartesian transmitter based on pulse width modulation, with the capability to drive a switched power amplifier, such as a Class D stage, is presented. A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is subsequently upconverted and applied to the output stage. This technique does not require a ramp generator or a high-precision voltage comparator, that are typically employed in conventional pulse width modulators. A prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a center frequency of 900 MHz. Operation of the architecture with modulation that has a non-constant envelope is verified in simulation.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2013.6571811</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.177-180 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_6571811 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth Cartesian Transmitters Frequency modulation Mixers PLL Pulse width modulation PWM Switches Transmitters WCDMA Wireless |
| title | Phase-locked loop based PWM wireless transmitter |
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