A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs
In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage a...
Gespeichert in:
Hauptverfasser: | , , , , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 132 |
---|---|
container_issue | |
container_start_page | 129 |
container_title | |
container_volume | |
creator | XiaoXin Cui KaiSheng Ma Kai Liao Nan Liao Di Wu Wei Wei Rui Li DunShan Yu |
description | In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately. |
doi_str_mv | 10.1109/ISCAS.2013.6571799 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6571799</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6571799</ieee_id><sourcerecordid>6571799</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-d42d8eb17db233fe53845f56fa1f20262487217ade8d786c3694c706848d161f3</originalsourceid><addsrcrecordid>eNpVkMtOwkAYRsdbIkFeQDfzAoPzz73LBkUxJC5At6R0_mmHlJZ0aghvL4lsXH2Lc3IWHyGPwKcAPHterGb5aio4yKnRFmyWXZFJZh0oY6W2Bsw1GQnQjoEW-uYf49ktGXFhgSnJxT2ZpLTjnJ-7BoQdkY-cvpzaYh9LlvvdTxpiW9F13WOqu8az764ZigrpqqxxjzR0PZ3Hdv66TrTpjvTQHbGnHlOs2vRA7kLRJJxcdky-zuLsnS0_3xazfMkiWD0wr4R3uAXrt0LKgFo6pYM2oYAguDBCOSvAFh6dt86U0mSqtNw45TwYCHJMnv66ERE3hz7ui_60uTwjfwEqBFFd</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>XiaoXin Cui ; KaiSheng Ma ; Kai Liao ; Nan Liao ; Di Wu ; Wei Wei ; Rui Li ; DunShan Yu</creator><creatorcontrib>XiaoXin Cui ; KaiSheng Ma ; Kai Liao ; Nan Liao ; Di Wu ; Wei Wei ; Rui Li ; DunShan Yu</creatorcontrib><description>In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 9781467357609</identifier><identifier>ISBN: 146735760X</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781467357616</identifier><identifier>EISBN: 1467357618</identifier><identifier>EISBN: 9781467357623</identifier><identifier>EISBN: 1467357626</identifier><identifier>DOI: 10.1109/ISCAS.2013.6571799</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; FinFETs ; Integrated circuit modeling ; Logic gates ; Phase locked loops ; Power dissipation ; Threshold voltage</subject><ispartof>2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.129-132</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6571799$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27912,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6571799$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>XiaoXin Cui</creatorcontrib><creatorcontrib>KaiSheng Ma</creatorcontrib><creatorcontrib>Kai Liao</creatorcontrib><creatorcontrib>Nan Liao</creatorcontrib><creatorcontrib>Di Wu</creatorcontrib><creatorcontrib>Wei Wei</creatorcontrib><creatorcontrib>Rui Li</creatorcontrib><creatorcontrib>DunShan Yu</creatorcontrib><title>A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs</title><title>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.</description><subject>Clocks</subject><subject>FinFETs</subject><subject>Integrated circuit modeling</subject><subject>Logic gates</subject><subject>Phase locked loops</subject><subject>Power dissipation</subject><subject>Threshold voltage</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9781467357609</isbn><isbn>146735760X</isbn><isbn>9781467357616</isbn><isbn>1467357618</isbn><isbn>9781467357623</isbn><isbn>1467357626</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtOwkAYRsdbIkFeQDfzAoPzz73LBkUxJC5At6R0_mmHlJZ0aghvL4lsXH2Lc3IWHyGPwKcAPHterGb5aio4yKnRFmyWXZFJZh0oY6W2Bsw1GQnQjoEW-uYf49ktGXFhgSnJxT2ZpLTjnJ-7BoQdkY-cvpzaYh9LlvvdTxpiW9F13WOqu8az764ZigrpqqxxjzR0PZ3Hdv66TrTpjvTQHbGnHlOs2vRA7kLRJJxcdky-zuLsnS0_3xazfMkiWD0wr4R3uAXrt0LKgFo6pYM2oYAguDBCOSvAFh6dt86U0mSqtNw45TwYCHJMnv66ERE3hz7ui_60uTwjfwEqBFFd</recordid><startdate>201305</startdate><enddate>201305</enddate><creator>XiaoXin Cui</creator><creator>KaiSheng Ma</creator><creator>Kai Liao</creator><creator>Nan Liao</creator><creator>Di Wu</creator><creator>Wei Wei</creator><creator>Rui Li</creator><creator>DunShan Yu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201305</creationdate><title>A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs</title><author>XiaoXin Cui ; KaiSheng Ma ; Kai Liao ; Nan Liao ; Di Wu ; Wei Wei ; Rui Li ; DunShan Yu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d42d8eb17db233fe53845f56fa1f20262487217ade8d786c3694c706848d161f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Clocks</topic><topic>FinFETs</topic><topic>Integrated circuit modeling</topic><topic>Logic gates</topic><topic>Phase locked loops</topic><topic>Power dissipation</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>XiaoXin Cui</creatorcontrib><creatorcontrib>KaiSheng Ma</creatorcontrib><creatorcontrib>Kai Liao</creatorcontrib><creatorcontrib>Nan Liao</creatorcontrib><creatorcontrib>Di Wu</creatorcontrib><creatorcontrib>Wei Wei</creatorcontrib><creatorcontrib>Rui Li</creatorcontrib><creatorcontrib>DunShan Yu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XiaoXin Cui</au><au>KaiSheng Ma</au><au>Kai Liao</au><au>Nan Liao</au><au>Di Wu</au><au>Wei Wei</au><au>Rui Li</au><au>DunShan Yu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs</atitle><btitle>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2013-05</date><risdate>2013</risdate><spage>129</spage><epage>132</epage><pages>129-132</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9781467357609</isbn><isbn>146735760X</isbn><eisbn>9781467357616</eisbn><eisbn>1467357618</eisbn><eisbn>9781467357623</eisbn><eisbn>1467357626</eisbn><abstract>In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2013.6571799</doi><tpages>4</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0271-4302 |
ispartof | 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.129-132 |
issn | 0271-4302 2158-1525 |
language | eng |
recordid | cdi_ieee_primary_6571799 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Clocks FinFETs Integrated circuit modeling Logic gates Phase locked loops Power dissipation Threshold voltage |
title | A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T14%3A43%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Dynamic-Adjusting%20Threshold-Voltage%20Scheme%20for%20FinFETs%20low%20power%20designs&rft.btitle=2013%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=XiaoXin%20Cui&rft.date=2013-05&rft.spage=129&rft.epage=132&rft.pages=129-132&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=9781467357609&rft.isbn_list=146735760X&rft_id=info:doi/10.1109/ISCAS.2013.6571799&rft_dat=%3Cieee_6IE%3E6571799%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467357616&rft.eisbn_list=1467357618&rft.eisbn_list=9781467357623&rft.eisbn_list=1467357626&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6571799&rfr_iscdi=true |