Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMO...

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Veröffentlicht in:	IEEE transactions on electron devices 2013-09, Vol.60 (9), p.2943-2950
Hauptverfasser:	Maheshwaram, Satish, Manhas, S. K., Kaushal, Gaurav, Anand, Bulusu, Singh, Navab
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Capacitance Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuit modeling Integrated circuits Inverter delay Logic gates Metals modeling MOS devices parasitic capacitance parasitic resistance Resistance Semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Theoretical study. Circuits analysis and design Transistors vertical nanowire MOSFET
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