Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis
In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMO...
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| Veröffentlicht in: | IEEE transactions on electron devices 2013-09, Vol.60 (9), p.2943-2950 |
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| container_title | IEEE transactions on electron devices |
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| creator | Maheshwaram, Satish Manhas, S. K. Kaushal, Gaurav Anand, Bulusu Singh, Navab |
| description | In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations. |
| doi_str_mv | 10.1109/TED.2013.2272651 |
| format | Article |
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Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.</description><subject>Applied sciences</subject><subject>Capacitance</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuits</subject><subject>Inverter delay</subject><subject>Logic gates</subject><subject>Metals</subject><subject>modeling</subject><subject>MOS devices</subject><subject>parasitic capacitance</subject><subject>parasitic resistance</subject><subject>Resistance</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Theoretical study. Circuits analysis and design</subject><subject>Transistors</subject><subject>vertical nanowire MOSFET</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1rAjEQxUNpodb2Xugllx7X5vvjKFbbglahttdljElJWXclEYr_vRHFywzDe2-Y-SH0SMmAUmJfluPXASOUDxjTTEl6hXpUSl1ZJdQ16hFCTWW54bfoLue_MiohWA9NfnzaRQcN_oS2-4_J49Fs_oUXkCDHouBZt_ZNbH8xtGscdxkvfApd2kDrPB620OxzzPfoJkCT_cO599H3ZLwcvVfT-dvHaDitHLN8V2oAZa0AsWLGOsqkWWkhtHTaOCcZcQG00dKvWFBBetDCE8Od5msQjAneR-S016Uu5-RDvU1xA2lfU1IfOdSFQ33kUJ85lMjzKbKFXP4MqRwe8yXHtNJaMFN8Tydf9N5fZCWVIkrwA5k_ZYA</recordid><startdate>20130901</startdate><enddate>20130901</enddate><creator>Maheshwaram, Satish</creator><creator>Manhas, S. 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Testing</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuits</topic><topic>Inverter delay</topic><topic>Logic gates</topic><topic>Metals</topic><topic>modeling</topic><topic>MOS devices</topic><topic>parasitic capacitance</topic><topic>parasitic resistance</topic><topic>Resistance</topic><topic>Semiconductor device modeling</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Theoretical study. Circuits analysis and design</topic><topic>Transistors</topic><topic>vertical nanowire MOSFET</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Maheshwaram, Satish</creatorcontrib><creatorcontrib>Manhas, S. K.</creatorcontrib><creatorcontrib>Kaushal, Gaurav</creatorcontrib><creatorcontrib>Anand, Bulusu</creatorcontrib><creatorcontrib>Singh, Navab</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maheshwaram, Satish</au><au>Manhas, S. K.</au><au>Kaushal, Gaurav</au><au>Anand, Bulusu</au><au>Singh, Navab</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2013-09-01</date><risdate>2013</risdate><volume>60</volume><issue>9</issue><spage>2943</spage><epage>2950</epage><pages>2943-2950</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2013.2272651</doi><tpages>8</tpages></addata></record> |
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| subjects | Applied sciences Capacitance Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuit modeling Integrated circuits Inverter delay Logic gates Metals modeling MOS devices parasitic capacitance parasitic resistance Resistance Semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Theoretical study. Circuits analysis and design Transistors vertical nanowire MOSFET |
| title | Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis |
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