Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology
Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technolog...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 56 |
|---|---|
| container_issue | |
| container_start_page | 53 |
| container_title | |
| container_volume | |
| creator | Moritz, Guillaume Giraud, Bastien Noel, Jean-Philippe Turgis, David Grover, Anuj |
| description | Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V. We use Flip-Well design methodology along with forward body bias modulation to extend operation range of the VSA and also reduce sense amplifier read time by 28%, while saving power consumption by up to 59% compared to Bulk technology. |
| doi_str_mv | 10.1109/ICICDT.2013.6563301 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6563301</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6563301</ieee_id><sourcerecordid>6563301</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-7c367e0efbdbac1036737df750c16ffa68651509ddf339cfbaa26e1a58aca8333</originalsourceid><addsrcrecordid>eNo9kE1uwjAQhd0_qZRyAja-QKgnju1kWaC0kZBYFNbIScbBbf4ahyJ6iV65qaDdvNHT92ZGeoSMgU0AWPQQz-LZfD3xGfCJFJJzBhfkDgKpeKACCC_JwJcReCyQ_hUZRSr8Y8y_7hkPweNCiFsycu6NMeYzBiBgQL5XTWdL-6U7W1e0NlTTz7rodI7UYeWQ6rIprLHY0rrBto9VObUV3Rddq-nBZvifb3XV68F2O5ro9J0mVjuaobN5RTtMd5X92KP7XfbDqqSb9XRKF3PvdRWfcF3U-fGe3BhdOByd55BsFk_r2Yu3XD3Hs8elZ0GJzlMplwoZmiTrfwHrHVeZUYKlII3RMpQCBIuyzHAepSbR2pcIWoQ61SHnfEjGp7sWEbdNa0vdHrfnbvkPDMNrSw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Moritz, Guillaume ; Giraud, Bastien ; Noel, Jean-Philippe ; Turgis, David ; Grover, Anuj</creator><creatorcontrib>Moritz, Guillaume ; Giraud, Bastien ; Noel, Jean-Philippe ; Turgis, David ; Grover, Anuj</creatorcontrib><description>Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V. We use Flip-Well design methodology along with forward body bias modulation to extend operation range of the VSA and also reduce sense amplifier read time by 28%, while saving power consumption by up to 59% compared to Bulk technology.</description><identifier>ISSN: 2381-3555</identifier><identifier>ISBN: 9781467347402</identifier><identifier>ISBN: 146734740X</identifier><identifier>EISSN: 2691-0462</identifier><identifier>EISBN: 1467347418</identifier><identifier>EISBN: 1467347434</identifier><identifier>EISBN: 9781467347419</identifier><identifier>EISBN: 9781467347433</identifier><identifier>DOI: 10.1109/ICICDT.2013.6563301</identifier><language>eng</language><publisher>IEEE</publisher><subject>Design methodology ; Logic gates ; MOS devices ; Optimization ; Power demand ; Random access memory ; Transistors</subject><ispartof>Proceedings of 2013 International Conference on IC Design & Technology (ICICDT), 2013, p.53-56</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6563301$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6563301$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Moritz, Guillaume</creatorcontrib><creatorcontrib>Giraud, Bastien</creatorcontrib><creatorcontrib>Noel, Jean-Philippe</creatorcontrib><creatorcontrib>Turgis, David</creatorcontrib><creatorcontrib>Grover, Anuj</creatorcontrib><title>Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology</title><title>Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)</title><addtitle>ICICDT</addtitle><description>Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V. We use Flip-Well design methodology along with forward body bias modulation to extend operation range of the VSA and also reduce sense amplifier read time by 28%, while saving power consumption by up to 59% compared to Bulk technology.</description><subject>Design methodology</subject><subject>Logic gates</subject><subject>MOS devices</subject><subject>Optimization</subject><subject>Power demand</subject><subject>Random access memory</subject><subject>Transistors</subject><issn>2381-3555</issn><issn>2691-0462</issn><isbn>9781467347402</isbn><isbn>146734740X</isbn><isbn>1467347418</isbn><isbn>1467347434</isbn><isbn>9781467347419</isbn><isbn>9781467347433</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kE1uwjAQhd0_qZRyAja-QKgnju1kWaC0kZBYFNbIScbBbf4ahyJ6iV65qaDdvNHT92ZGeoSMgU0AWPQQz-LZfD3xGfCJFJJzBhfkDgKpeKACCC_JwJcReCyQ_hUZRSr8Y8y_7hkPweNCiFsycu6NMeYzBiBgQL5XTWdL-6U7W1e0NlTTz7rodI7UYeWQ6rIprLHY0rrBto9VObUV3Rddq-nBZvifb3XV68F2O5ro9J0mVjuaobN5RTtMd5X92KP7XfbDqqSb9XRKF3PvdRWfcF3U-fGe3BhdOByd55BsFk_r2Yu3XD3Hs8elZ0GJzlMplwoZmiTrfwHrHVeZUYKlII3RMpQCBIuyzHAepSbR2pcIWoQ61SHnfEjGp7sWEbdNa0vdHrfnbvkPDMNrSw</recordid><startdate>201305</startdate><enddate>201305</enddate><creator>Moritz, Guillaume</creator><creator>Giraud, Bastien</creator><creator>Noel, Jean-Philippe</creator><creator>Turgis, David</creator><creator>Grover, Anuj</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201305</creationdate><title>Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology</title><author>Moritz, Guillaume ; Giraud, Bastien ; Noel, Jean-Philippe ; Turgis, David ; Grover, Anuj</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7c367e0efbdbac1036737df750c16ffa68651509ddf339cfbaa26e1a58aca8333</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Design methodology</topic><topic>Logic gates</topic><topic>MOS devices</topic><topic>Optimization</topic><topic>Power demand</topic><topic>Random access memory</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Moritz, Guillaume</creatorcontrib><creatorcontrib>Giraud, Bastien</creatorcontrib><creatorcontrib>Noel, Jean-Philippe</creatorcontrib><creatorcontrib>Turgis, David</creatorcontrib><creatorcontrib>Grover, Anuj</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Moritz, Guillaume</au><au>Giraud, Bastien</au><au>Noel, Jean-Philippe</au><au>Turgis, David</au><au>Grover, Anuj</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology</atitle><btitle>Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)</btitle><stitle>ICICDT</stitle><date>2013-05</date><risdate>2013</risdate><spage>53</spage><epage>56</epage><pages>53-56</pages><issn>2381-3555</issn><eissn>2691-0462</eissn><isbn>9781467347402</isbn><isbn>146734740X</isbn><eisbn>1467347418</eisbn><eisbn>1467347434</eisbn><eisbn>9781467347419</eisbn><eisbn>9781467347433</eisbn><abstract>Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V. We use Flip-Well design methodology along with forward body bias modulation to extend operation range of the VSA and also reduce sense amplifier read time by 28%, while saving power consumption by up to 59% compared to Bulk technology.</abstract><pub>IEEE</pub><doi>10.1109/ICICDT.2013.6563301</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2381-3555 |
| ispartof | Proceedings of 2013 International Conference on IC Design & Technology (ICICDT), 2013, p.53-56 |
| issn | 2381-3555 2691-0462 |
| language | eng |
| recordid | cdi_ieee_primary_6563301 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Design methodology Logic gates MOS devices Optimization Power demand Random access memory Transistors |
| title | Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T23%3A34%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Optimization%20of%20a%20voltage%20sense%20amplifier%20operating%20in%20ultra%20wide%20voltage%20range%20with%20back%20bias%20design%20techniques%20in%2028nm%20UTBB%20FD-SOI%20technology&rft.btitle=Proceedings%20of%202013%20International%20Conference%20on%20IC%20Design%20&%20Technology%20(ICICDT)&rft.au=Moritz,%20Guillaume&rft.date=2013-05&rft.spage=53&rft.epage=56&rft.pages=53-56&rft.issn=2381-3555&rft.eissn=2691-0462&rft.isbn=9781467347402&rft.isbn_list=146734740X&rft_id=info:doi/10.1109/ICICDT.2013.6563301&rft_dat=%3Cieee_6IE%3E6563301%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467347418&rft.eisbn_list=1467347434&rft.eisbn_list=9781467347419&rft.eisbn_list=9781467347433&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6563301&rfr_iscdi=true |