Power-simulation of cell based ASICs: accuracy- and performance trade-offs
Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these m...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 361 |
|---|---|
| container_issue | |
| container_start_page | 356 |
| container_title | |
| container_volume | |
| creator | Rabe, D. Jochens, G. Kruse, L. Nebel, W. |
| description | Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level. |
| doi_str_mv | 10.1109/DATE.1998.655882 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_655882</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>655882</ieee_id><sourcerecordid>655882</sourcerecordid><originalsourceid>FETCH-LOGICAL-i214t-59daae76e999e2a99ffa00cef111c22aca9702fde7f5e799244cf4cff09817b63</originalsourceid><addsrcrecordid>eNotj11LwzAUhgMiKLP34lX-QGqSNh_Hu1KnTgYKzutxlp5ApV1H0iH79w7mywPP3QMvY_dKlkpJeHxuNstSAfjSGuO9vmIFOC-98tZXBuwNK3L-kedVUCtrbtn75_RLSeR-PA4499OeT5EHGga-w0wdb75WbX7iGMIxYTgJjvuOHyjFKY24D8TnhB2JKcZ8x64jDpmKfy_Y98ty076J9cfrqm3WoteqnoWBDpGcJQAgjQAxopSBolIqaI0BwUkdO3LRkAPQdR3imSjBK7ez1YI9XLo9EW0PqR8xnbaXw9UfQyNLvA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Power-simulation of cell based ASICs: accuracy- and performance trade-offs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Rabe, D. ; Jochens, G. ; Kruse, L. ; Nebel, W.</creator><creatorcontrib>Rabe, D. ; Jochens, G. ; Kruse, L. ; Nebel, W.</creatorcontrib><description>Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.</description><identifier>ISBN: 9780818683596</identifier><identifier>ISBN: 0818683597</identifier><identifier>DOI: 10.1109/DATE.1998.655882</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; Circuit simulation ; Computational modeling ; Computer science ; Computer simulation ; Delay estimation ; Energy consumption ; Hardware design languages ; Integrated circuit reliability ; Voltage</subject><ispartof>Proceedings Design, Automation and Test in Europe, 1998, p.356-361</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/655882$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/655882$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rabe, D.</creatorcontrib><creatorcontrib>Jochens, G.</creatorcontrib><creatorcontrib>Kruse, L.</creatorcontrib><creatorcontrib>Nebel, W.</creatorcontrib><title>Power-simulation of cell based ASICs: accuracy- and performance trade-offs</title><title>Proceedings Design, Automation and Test in Europe</title><addtitle>DATE</addtitle><description>Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.</description><subject>Application specific integrated circuits</subject><subject>Circuit simulation</subject><subject>Computational modeling</subject><subject>Computer science</subject><subject>Computer simulation</subject><subject>Delay estimation</subject><subject>Energy consumption</subject><subject>Hardware design languages</subject><subject>Integrated circuit reliability</subject><subject>Voltage</subject><isbn>9780818683596</isbn><isbn>0818683597</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj11LwzAUhgMiKLP34lX-QGqSNh_Hu1KnTgYKzutxlp5ApV1H0iH79w7mywPP3QMvY_dKlkpJeHxuNstSAfjSGuO9vmIFOC-98tZXBuwNK3L-kedVUCtrbtn75_RLSeR-PA4499OeT5EHGga-w0wdb75WbX7iGMIxYTgJjvuOHyjFKY24D8TnhB2JKcZ8x64jDpmKfy_Y98ty076J9cfrqm3WoteqnoWBDpGcJQAgjQAxopSBolIqaI0BwUkdO3LRkAPQdR3imSjBK7ez1YI9XLo9EW0PqR8xnbaXw9UfQyNLvA</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Rabe, D.</creator><creator>Jochens, G.</creator><creator>Kruse, L.</creator><creator>Nebel, W.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1998</creationdate><title>Power-simulation of cell based ASICs: accuracy- and performance trade-offs</title><author>Rabe, D. ; Jochens, G. ; Kruse, L. ; Nebel, W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i214t-59daae76e999e2a99ffa00cef111c22aca9702fde7f5e799244cf4cff09817b63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Application specific integrated circuits</topic><topic>Circuit simulation</topic><topic>Computational modeling</topic><topic>Computer science</topic><topic>Computer simulation</topic><topic>Delay estimation</topic><topic>Energy consumption</topic><topic>Hardware design languages</topic><topic>Integrated circuit reliability</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Rabe, D.</creatorcontrib><creatorcontrib>Jochens, G.</creatorcontrib><creatorcontrib>Kruse, L.</creatorcontrib><creatorcontrib>Nebel, W.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rabe, D.</au><au>Jochens, G.</au><au>Kruse, L.</au><au>Nebel, W.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power-simulation of cell based ASICs: accuracy- and performance trade-offs</atitle><btitle>Proceedings Design, Automation and Test in Europe</btitle><stitle>DATE</stitle><date>1998</date><risdate>1998</risdate><spage>356</spage><epage>361</epage><pages>356-361</pages><isbn>9780818683596</isbn><isbn>0818683597</isbn><abstract>Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.</abstract><pub>IEEE</pub><doi>10.1109/DATE.1998.655882</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9780818683596 |
| ispartof | Proceedings Design, Automation and Test in Europe, 1998, p.356-361 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_655882 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits Circuit simulation Computational modeling Computer science Computer simulation Delay estimation Energy consumption Hardware design languages Integrated circuit reliability Voltage |
| title | Power-simulation of cell based ASICs: accuracy- and performance trade-offs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T05%3A40%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Power-simulation%20of%20cell%20based%20ASICs:%20accuracy-%20and%20performance%20trade-offs&rft.btitle=Proceedings%20Design,%20Automation%20and%20Test%20in%20Europe&rft.au=Rabe,%20D.&rft.date=1998&rft.spage=356&rft.epage=361&rft.pages=356-361&rft.isbn=9780818683596&rft.isbn_list=0818683597&rft_id=info:doi/10.1109/DATE.1998.655882&rft_dat=%3Cieee_6IE%3E655882%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=655882&rfr_iscdi=true |